參數(shù)資料
型號: CY7C1041CV33-15VXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4-Mbit (256K x 16) Static RAM
中文描述: 256K X 16 STANDARD SRAM, 15 ns, PDSO44
封裝: 0.400 INCH, LEAD FREE, SOJ-44
文件頁數(shù): 6/12頁
文件大?。?/td> 595K
代理商: CY7C1041CV33-15VXI
CY7C1041CV33
Document #: 38-05134 Rev. *H
Page 6 of 12
Write Cycle
[9, 10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[7]
WE LOW to High-Z
[7, 8]
Byte Enable to End of Write
10
7
7
0
0
7
5
0
3
12
8
8
0
0
8
6
0
3
15
10
10
0
0
10
7
0
3
20
10
10
0
0
10
8
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
6
7
8
7
8
10
10
Switching Waveforms
Read Cycle No. 1
[11, 12]
Read Cycle No. 2 (OE Controlled)
[12, 13]
Notes:
10.The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
11.Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
12.WE is HIGH for Read cycle.
13.Address valid prior to or coincident with CE transition LOW.
AC Switching Characteristics
[5]
Over the Operating Range (continued)
Parameter
Description
-10
-12
-15
-20
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZBE
t
PD
HIGH
OE
CE
ICC
I
I
SB
IMPEDANCE
ADDRESS
DATA OUT
V
SUPPLY
CURRENT
t
DBE
t
LZBE
t
HZCE
BHE, BLE
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相關(guān)PDF資料
PDF描述
CY7C1041CV33-15ZXC 4-Mbit (256K x 16) Static RAM
CY7C1041CV33-15ZXI 4-Mbit (256K x 16) Static RAM
CY7C1041CV33-20VE 4-Mbit (256K x 16) Static RAM
CY7C1041CV33-20VXE 4-Mbit (256K x 16) Static RAM
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