參數(shù)資料
型號: CY7C1041CV33-12ZXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4-Mbit (256K x 16) Static RAM
中文描述: 256K X 16 STANDARD SRAM, 12 ns, PDSO44
封裝: LEAD FREE, TSOP2-44
文件頁數(shù): 3/12頁
文件大小: 595K
代理商: CY7C1041CV33-12ZXI
CY7C1041CV33
Document #: 38-05134 Rev. *H
Page 3 of 12
Pin Definitions
Pin Name
A
0
–A
17
44-SOJ,
44-TSOP
Pin Number
1–5, 18–27,
42–44
48-ball FBGA
Pin Number
A3, A4, A5, B3,
B4, C3, C4, D4,
H2, H3, H4, H5,
G3, G4, F3, F4,
E4, D3
B1, C1, C2, D2,
E2, F2, F1, G1,
B6, C6, C5, D5,
E5, F5, F6, G6
A6, E3, G2, H1,
H6
G5
I/O Type
Input
Description
Address Inputs used to select one of the address
locations.
I/O
0
–I/O
15
7–10,13–16,
29–32, 35–38
Input/Output
Bidirectional Data I/O lines.
Used as input or output lines
depending on operation
NC
28
No Connect
No Connects.
This pin is not connected to the die
WE
17
Input/Control
Write Enable Input, active LOW.
When selected LOW, a
WRITE is conducted. When selected HIGH, a READ is
conducted.
Input/Control
Chip Enable Input, active LOW.
When LOW, selects the chip.
When HIGH, deselects the chip.
Input/Control
Byte Write Select Inputs, active LOW.
BHE controls
I/O
15
–I/O
8
, BLE controls I/O
7
–I/O
0
Input/Control
Output Enable, active LOW.
Controls the direction of the I/O
pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and
act as input data pins.
Ground
Ground for the device.
Should be connected to ground of the
system.
Power Supply
Power Supply inputs to the device.
CE
6
B5
BHE, BLE
40, 39
B2, A1
OE
41
A2
V
SS
12, 34
D1, E6
V
CC
11, 33
D6, E1
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CY7C1041CV33-15VXC 4-Mbit (256K x 16) Static RAM
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CY7C1041CV33-15ZXC 4-Mbit (256K x 16) Static RAM
CY7C1041CV33-15ZXI 4-Mbit (256K x 16) Static RAM
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