參數(shù)資料
型號(hào)： CY7C1041BV33-25VI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 256K x 16 Static RAM
中文描述： 256K X 16 STANDARD SRAM, 25 ns, PDSO44
封裝： 0.400 INCH, PLASTIC, SOJ-44
文件頁(yè)數(shù)： 1/11頁(yè)
文件大小： 187K
代理商： CY7C1041BV33-25VI
256K x 16 Static RAM
CY7C1041BV33
Cypress Semiconductor Corporation
Document #: 38-05168 Rev. **
3901 North First Street
San Jose
CA 95134
Revised November 15, 2001
408-943-2600
041BV33
Features
High speed
—t
AA
= 12 ns
Low active power
—612 mW (max.)
Low CMOS standby power (Commercial L version)
—1.8 mW (max.)
2.0V Data Retention (600
μ
W at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
The CY7C1041BV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041BV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
1
A
1
A
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
256K x 16
ARRAY
1024 x 4096
A
0
A
1
A
1
A
1
A
1
A
1
A
9
A
1
I/O
0
–
I/O
7
BLE
I/O
8
–
I/O
15
OE
WE
Top View
SOJ
TSOP II
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
4
I/O
5
A
0
A
1
A
2
A
3
A
4
OE
BHE
BLE
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
17
A
16
A
15
I/O
15
I/O
14
I/O
13
I/O
12
CE
I/O
0
I/O
1
I/O
2
I/O
3
18
19
20
21
27
26
25
24
22
23
I/O
6
I/O
7
A
14
A
13
A
12
A
11
A
10
Selection Guide
-12
12
190
-
8
0.5
-15
15
170
190
8
0.5
-17
17
160
180
8
0.5
-20
20
150
170
8
0.5
-25
25
130
150
8
0.5
Maximum Access Time (ns)
Maximum Operating Current (mA) Comm
’
l
Ind
’
l
Com
’
l/Ind
’
l
Com
’
l
Maximum CMOS Standby
Current (mA)
L
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