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參數(shù)資料
| 型號： | CY7C1031-10NC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 64K X 18 CACHE SRAM, 10 ns, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 343K |
| 代理商： | CY7C1031-10NC |
CY7C1031
CY7C1032
PRELIMINARY
12
Output Timing (Controlled by CS)
Output Timing (Controlled by WH/ WL)
Switching Waveforms (continued)
tCSS
tCSH
1031–12
tCSS
tCSH
tCDV
tCSOZ
CLK
CS
DATA OUT
tADS
tADSH
tADS
tADSH
ADSC
tADS
1031–13
CLK
tWEOZ
tWEOV
WH, WL
DATA OUT
tWES
tWEH
tADSH
ADSC and
ADSP
Truth Table
Input
CS
ADSP
ADSC
ADV
WH or WL
CLK
Address
Operation
H
X
L
X
L
→H
N/A
Chip deselected
H
L
H
L
→H
Same address as
previous cycle
Read cycle (ADSP ignored)
H
L
H
L
H
L
→H
Incremented burst
address
Read cycle, in burst sequence
(ADSP ignored)
H
L
H
L
→H
Same address as
previous cycle
Write cycle (ADSP ignored)
H
L
H
L
→H
Incremented burst
address
Write cycle, in burst sequence
(ADSP ignored)
L
X
L
→H
External
Read cycle, begin burst
L
H
L
X
H
L
→H
External
Read cycle, begin burst
L
H
L
X
L
→H
External
Write cycle, begin burst
X
H
L
→H
Incremented burst
address
Write cycle, in burst sequence
X
H
L
H
L
→H
Incremented burst
address
Read cycle, in burst sequence
X
H
L
→H
Same address as
previous cycle
Write cycle
X
H
L
→H
Same address as
previous cycle
Read cycle
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| CY7C1031-12JCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 5V 1.125M-Bit 64K x 18 12ns 52-Pin PLCC T/R |
| CY7C1031-8JC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1031-8JCT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1032-10JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 5V 1.125M-Bit 64K x 18 10ns 52-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:1MB (64KX18) SYNCH RAM POWER PC BURST - Bulk |
| CY7C1032-10JCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 5V 1.125M-Bit 64K x 18 10ns 52-Pin PLCC T/R |
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