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參數(shù)資料
| 型號(hào)： | CY7C1021D |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1-Mbit (64K x 16) Static RAM |
| 中文描述： | 1兆位（64K的× 16）靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大小： | 479K |
| 代理商： | CY7C1021D |
CY7C1021D
1-Mbit (64K x 16) Static RAM
Cypress Semiconductor Corporation
Document #: 38-05462 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised February 22, 2007
Features
Pin-and function-compatible with CY7C1021B
High speed
— t
AA
= 10 ns
Low active power
— I
CC
= 80 mA @ 10 ns
Low CMOS Standby Power
— I
SB2
= 3 mA
2.0V Data Retention
Automatic power-down when deselected
CMOS for optimum speed/power
Independent control of upper and lower bits
Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin TSOP II packages
Functional Description
[1]
The CY7C1021D is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected. The input/output pins
(IO
0
through IO
15
) are placed in a high-impedance state when:
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
BHE and BLE are disabled (BHE, BLE HIGH)
When the write operation is active (CE LOW, and WE LOW)
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW,
then data from IO pins (IO
0
through IO
7
), is written into the
location specified on the address pins (A
0
through A
15
). If Byte
High Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
) is written into the location specified on the
address pins (A
0
through A
15
).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO
0
to IO
7
.
If Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. See the
“Truth Table” on page 8
for a
complete description of read and write modes.
Logic Block Diagram
64K x 16
RAM Array
IO
0
–IO
7
R
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
A
9
A
1
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
IO
8
–IO
15
CE
WE
BHE
A
8
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at
www.cypress.com
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1021D-10VXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1M 512K IND FAST ASYNC 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1021D-10VXI | 制造商:Cypress Semiconductor 功能描述:IC SRAM 1MBIT PARALLEL 10NS SOJ-44 |
| CY7C1021D10VXIT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1021D-10VXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1M 512K IND FAST ASYNC 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1021D-10ZSXA | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1-Mbit 64k x16 Static RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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