參數(shù)資料
型號(hào)： CY7C1021BNV33L-12ZXC
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 64K x 16 Static RAM
中文描述： 64K X 16 STANDARD SRAM, 12 ns, PDSO44
封裝： LEAD FREE, TSOP2-44
文件頁(yè)數(shù)： 4/10頁(yè)
文件大?。?/td> 530K
代理商： CY7C1021BNV33L-12ZXC
CY7C1021BNV33
Document #: 001-06433 Rev. **
Page 4 of 10
Switching Characteristics
[3]
Over the Operating Range
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
[6]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Data Retention Characteristics
Over the Operating Range (L version only)
Parameter
Description
V
DR
V
CC
for Data Retention
I
CCDR
Data Retention Current
Description
-10
-12
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[4, 5]
CE LOW to Low Z
[5]
CE HIGH to High Z
[4, 5]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
15
3
3
3
10
4
12
6
15
7
0
0
0
5
6
7
3
3
3
5
6
7
0
0
0
12
5
12
6
15
7
0
0
0
5
6
7
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[5]
WE LOW to High Z
[4, 5]
Byte Enable to End of Write
10
8
7
0
0
8
6
0
3
12
9
8
0
0
8
6
0
3
15
10
10
0
0
10
8
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
6
7
8
8
9
Conditions
[7]
Min.
2.0
Max.
Unit
V
μ
A
Com’l
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
100
t
CDR[8]
t
R[9]
Notes:
3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
4. t
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state
voltage.
5. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
6. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a
write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
7. No input may exceed V
+ 0.5V.
8. Tested initially and after any design or process changes that may affect these parameters.
9. t
r
< 3 ns for the -12 and -15 speeds. t
r
< 5 ns for the -20 and slower speeds.
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
t
RC
[+] Feedback
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CY7C1021BNV33L-12ZXCT 功能描述:IC SRAM 1MBIT 12NS 44TSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱(chēng):557-1327-2
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CY7C1021BNV33L-15BAIT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 64K x 16 ASYNC 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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