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參數(shù)資料
| 型號(hào)： | CY7C1020CV33-10ZXCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 32K X 16 STANDARD SRAM, 10 ns, PDSO44 |
| 封裝： | LEAD FREE, TSOP2-44 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大小： | 133K |
| 代理商： | CY7C1020CV33-10ZXCT |
CY7C1020CV33
Document #: 38-05133 Rev. *D
Page 4 of 9
AC Test Loads and Waveforms[4]
Switching Characteristics Over the Operating Range[4]
Parameter
Description
1020CV33-10
1020CV33-12
1020CV33-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
10
12
15
ns
tOHA
Data Hold from Address Change
3
ns
tACE
CE LOW to Data Valid
10
12
15
ns
tDOE
OE LOW to Data Valid
5
6
7
ns
tLZOE
OE LOW to Low-Z[5]
000
ns
tHZOE
OE HIGH to High-Z[5, 6]
567
ns
tLZCE
CE LOW to Low-Z[5]
333
ns
tHZCE
CE HIGH to High-Z[5, 6]
567
ns
tPU
[7]
CE LOW to Power-up
0
ns
tPD
[7]
CE HIGH to Power-down
10
12
15
ns
tDBE
Byte Enable to Data Valid
5
6
7
ns
tLZBE
Byte Enable to Low-Z
0
ns
tHZBE
Byte Disable to High-Z
5
6
7
ns
Write Cycle[8]
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
8
9
10
ns
tAW
Address Set-up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Set-up to Write End
5
6
8
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low-Z[5]
333
ns
tHZWE
WE LOW to High-Z[5, 6]
567
ns
tBW
Byte Enable to End of Write
7
8
9
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. This parameter is guaranteed by design and is not tested.
8. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
R 317
R2
351
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(b)
(a)
3.3V
OUTPUT
5 pF
(c)
R 317
R2
351
High-Z characteristics:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1020CV33-12ZC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 512K-Bit 32K x 16 12ns 44-Pin TSOP-II |
| CY7C1020CV33-12ZCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 512K-Bit 32K x 16 12ns 44-Pin TSOP-II T/R |
| CY7C1020CV33-15BAXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1020CV33-15ZC | 功能描述:IC SRAM 512KBIT 15NS 44TSOP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1020CV33-15ZCT | 制造商:Cypress Semiconductor 功能描述: |
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