參數(shù)資料
型號(hào)： CY7C1020-20VC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 32K x 16 Static RAM
中文描述： 32K X 16 STANDARD SRAM, 20 ns, PDSO44
封裝： 0.400 INCH, PLASTIC, SOJ-44
文件頁數(shù)： 3/8頁
文件大?。?/td> 147K
代理商： CY7C1020-20VC
CY7C1020CV33
Document #: 38-05133 Rev. *B
Page 3 of 8
AC Test Loads and Waveforms
[4]
Switching Characteristics
Over the Operating Range
[4]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU[7]
t
PD[7]
t
DBE
t
LZBE
t
HZBE
Write Cycle
[8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
6.
t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
7.
This parameter is guaranteed by design and is not tested.
8.
The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Description
1020CV33-10
Min.
1020CV33-12
Min.
1020CV33-15
Min.
Unit
Max.
Max.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[5]
OE HIGH to High-Z
[5, 6]
CE LOW to Low-Z
[5]
CE HIGH to High-Z
[5, 6]
CE LOW to Power-up
CE HIGH to Power-down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
15
3
3
3
10
5
12
6
15
7
0
0
0
5
6
7
3
3
3
5
6
7
0
0
0
10
5
12
6
15
7
0
0
0
5
6
7
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[5]
WE LOW to High-Z
[5, 6]
Byte Enable to End of Write
10
8
7
0
0
7
5
0
3
12
9
8
0
0
8
6
0
3
15
10
10
0
0
10
8
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
6
7
7
8
9
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
R 317
R2
351
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(b)
(a)
3.3V
OUTPUT
5 pF
(c)
R 317
R2
351
High-Z characteristics:
相關(guān)PDF資料
PDF描述
CY7C1020-20ZC 32K x 16 Static RAM
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CY7C1020L-10ZC 32K x 16 Static RAM
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CY7C1020L-12ZC 32K x 16 Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1020B-12VC 制造商:Rochester Electronics LLC 功能描述:512K (32K X 16)- FAST ASYNCH SRAM - Bulk
CY7C1020B-12VXC 功能描述:IC SRAM 512KBIT 12NS 44SOJ RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2
CY7C1020B-12VXCT 功能描述:IC SRAM 512KBIT 12NS 44SOJ RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2
CY7C1020B-12ZC 制造商:Rochester Electronics LLC 功能描述:512K (32K X 16)- FAST ASYNCH SRAM - Bulk
CY7C1020B-12ZXC 功能描述:IC SRAM 512KBIT 12NS 44TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2
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