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參數(shù)資料
| 型號： | CY7C1018DV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1-Mbit (128K x 8) Static RAM(1Mbit (128K x 8)靜態(tài)RAM) |
| 中文描述： | 1兆位（128K的× 8）靜態(tài)隨機(jī)存儲(chǔ)器（容量為1Mbit（128K的× 8）靜態(tài)的RAM） |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 256K |
| 代理商： | CY7C1018DV33 |
1-Mbit (128K x 8) Static RAM
CY7C1018DV33
Cypress Semiconductor Corporation
Document #: 38-05465 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised November 8, 2006
Features
Pin- and function-compatible with CY7C1018CV33
High speed
— t
AA
= 10 ns
Low Active Power
— I
CC
= 60 mA @ 10 ns
Low CMOS Standby Power
— I
SB2
= 3 mA
2.0V Data retention
Automatic power-down when deselected
CMOS for optimum speed/power
Center power/ground pinout
Easy memory expansion with CE
and OE options
Available in Pb-free 32-pin 300-Mil wide Molded SOJ
Functional Description
[1]
The CY7C1018DV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil
wide Molded SOJ.
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
9
A
1
128K × 8
ARRAY
A
1
A
1
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
18
20
24
23
22
21
25
28
27
26
Top View
SOJ
29
32
31
30
16
17
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
V
SS
A
13
OE
I/O
7
I/O
6
V
SS
A
16
A
15
A
14
A
12
A
11
A
10
A
9
A
8
I/O
2
I/O
3
WE
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
Pin Configuration
Note
1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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| CY7C1019BV33L-12VC | 128K x 8 Static RAM |
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| CY7C1019V33-10VC | 128K x 8 Static RAM |
| CY7C1019V33-12VC | 128K x 8 Static RAM |
| CY7C1019V33-15VC | 128K x 8 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1018DV33-10VXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1M 512K IND FAST ASYNC 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1018DV33-10VXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1M 512K IND FAST ASYNC 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1018V33-12VC | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3.3V 1MBIT 128KX8 12NS 32PIN MLD SOJ - Bulk |
| CY7C1019B-10VC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1019B-10VCT | 制造商:Cypress Semiconductor 功能描述: |
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