參數(shù)資料
型號(hào): CY7C1018CV33-15VC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 128K x 8 Static RAM
中文描述: 128K X 8 STANDARD SRAM, 15 ns, PDSO32
封裝: 0.300 INCH, SOJ-32
文件頁(yè)數(shù): 3/7頁(yè)
文件大小: 132K
代理商: CY7C1018CV33-15VC
CY7C1018CV33
Document #: 38-05131 Rev. *C
Page 3 of 7
AC Test Loads and Waveforms
[5]
Switching Characteristics
Over the Operating Range
[6]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
Description
7C1018CV33-8
Min.
7C1018CV33-10 7C1018CV33-12 7C1018CV33-15
Min.
Max.
Min.
Unit
Max.
Max.
Min.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address
Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[7, 8]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[7, 8]
CE LOW to Power-up
CE HIGH to Power-down
8
10
12
15
ns
ns
ns
8
10
12
15
3
3
3
3
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU[9]
t
PD[9]
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
5.
AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Th
è
venin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
6.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7.
t
, t
, and t
are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8.
At any given temperature and voltage condition, t
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9.
This parameter is guaranteed by design and is not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11.
The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
8
5
10
5
12
6
15
7
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
4
5
6
7
3
3
3
3
4
5
6
7
0
0
0
0
8
10
12
15
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[8]
WE LOW to High-Z
[7, 8]
8
7
7
0
0
6
5
0
3
10
8
8
0
0
7
5
0
3
12
9
9
0
0
8
6
0
3
15
10
10
0
0
10
8
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
5
6
7
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
(b)
R 317
R2
351
Rise Time: 1 V/ns
Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5V
(c)
(a)
3.3V
OUTPUT
5 pF
(d)
R 317
R2
351
8-ns devices:
10-, 12-, 15-ns devices:
High-Z characteristics:
相關(guān)PDF資料
PDF描述
CY7C1018CV33-8VC 128K x 8 Static RAM
CY7C1020CV33-10ZC 32K x 16 Static RAM
CY7C1020-12ZC 32K x 16 Static RAM
CY7C1020-15VC 32K x 16 Static RAM
CY7C1020-15ZC 32K x 16 Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1018CV33-15VXC 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C1018CV33-8VC 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3.3V 1MBIT 128KX8 8NS 32PIN MLD SOJ - Bulk
CY7C1018CV33-8VCT 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3.3V 1MBIT 128KX8 8NS 32PIN MLD SOJ - Tape and Reel
CY7C1018DV33-10VXI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1M 512K IND FAST ASYNC 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1018DV33-10VXIT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1M 512K IND FAST ASYNC 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray