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參數(shù)資料
| 型號(hào)： | CY7C1016V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 16Kx9 Dual-Port Static RAM(3.3V 16Kx 9 位雙端口靜態(tài)RAM) |
| 中文描述： | 3.3 16Kx9雙端口靜態(tài)RAM（3.3 16Kx 9位雙端口靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 1/22頁(yè) |
| 文件大?。?/td> | 308K |
| 代理商： | CY7C1016V |
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PRELIMINARY
3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
November 30, 1999
1
Features
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
4K/8K/16K/32K x 8 organizations (CY7C0138V/144V/
006V/007V)
4K/8K/16K/32K x 9 organizations (CY7C0139V/145V/
016V/017V)
0.35-micron CMOS for optimum speed/power
High-speed access: 15
[1]
/20/25 ns
Low operating power
—Active: I
CC
= 115 mA (typical)
—Standby: I
SB3
= 10
μ
A (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 16/18 bits or more using Master/
Slave chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Pin select for Master or Slave
Commercial and Industrial Temperature Ranges
Available in 68-pin PLCC (all), 64-pin TQFP (7C006V &
7C144V)
Pin-compatible and functionally equivalent to
IDT70V05, 70V06, and 70V07.
Notes:
1.
2.
3.
4.
Call for availability
I/O
0
–I/O
for x8 devices; I/O
0
–I/O
for x9 devices.
A
–A
for 4K devices; A
–A
for 8K devices; A
–A
for 16K devices; A
0
–A
14
for 32K devices.
BUSY is an output in master mode and an input in slave mode.
I/O
Control
Address
Decode
A
0L
–A
11–14L
CE
L
OE
L
R/W
L
SEM
L
BUSY
L
INT
L
I/O
Control
Interrupt
Semaphore
Arbitration
M/S
A
0L
–A
11–14L
True Dual-Ported
RAM Array
A
0R
–A
11–14R
CE
R
OE
R
R/W
R
SEM
R
BUSY
R
INT
R
Address
Decode
A
0R
–A
11–14R
[2]
[2]
[4]
[4]
R/W
L
OE
L
I/O
0L
–I/O
7/8L
CE
L
R/W
R
OE
R
I/O
0R
–I/O
7/8R
CE
R
12–15
8/9
12–15
8/9
12–15
12–15
[3]
[3]
[3]
[3]
Logic Block Diagram
For the most recent information, visit the Cypress web site at www.cypress.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C138V | 3.3V 4Kx 8 Dual-Port Static RAM(3.3V 4Kx 8 位雙端口靜態(tài)RAM) |
| CY7C139V | 3.3V 4Kx9 Dual-Port Static RAM(3.3V 4Kx 9 位雙端口靜態(tài)RAM) |
| CY7C144V | 3.3V 8Kx 8 Dual-Port Static RAM(3.3V 8Kx 8位 雙端口靜態(tài)RAM) |
| CY7C007V | 3.3V 32K x 8 Dual-Port Static RAM(3.3V 32Kx 8位 雙端口靜態(tài)RAM) |
| CY7C017V | 3.3V 32K x9 Dual-Port Static RAM(3.3V 32Kx 9 位雙端口靜態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1018BV33-12VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 12ns 32-Pin SOJ 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1018BV33-12VCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 12ns 32-Pin SOJ T/R 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY7C1018BV33-15VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1018CV33-10VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 10ns 32-Pin SOJ |
| CY7C1018CV33-10VCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 10ns 32-Pin SOJ T/R |
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