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參數(shù)資料
| 型號(hào)： | CY7C1010DV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2-Mbit (256K x 8)Static RAM(2Mbit (256K x 8)靜態(tài)RAM) |
| 中文描述： | 2兆位（256K × 8）靜態(tài)隨機(jī)存儲(chǔ)器（2Mbit的（256K × 8）靜態(tài)的RAM） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 345K |
| 代理商： | CY7C1010DV33 |
2-Mbit (256K x 8)Static RAM
CY7C1010DV33
Cypress Semiconductor Corporation
Document #: 001-00062 Rev. *A
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 17, 2006
Features
Pin and function compatible with CY7C1010CV33
High speed
— t
AA
= 10 ns
Low active power
— I
CC
= 90 mA @ 10 ns
Low CMOS standby power
— I
SB2
= 10 mA
2.0V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Lead-Free 44-pin TSOP II package
Functional Description
[1]
The CY7C1010DV33 is a high-performance CMOS Static
RAM organized as 256K words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1010DV33 is available in standard 44-pin TSOP II
package with center power and ground (revolutionary) pinout.
Selection Guide
–10
10
90
10
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note:
1. For guidelines on SRAM system design, please refer to the
System Design Guidelines
Cypress application note, available on the internet at www.cypress.com
1
A
1
A
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
256K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
CE
A
1
A
1
Logic Block Diagram
Pin Configuration
A
16
A
15
A
14
A
13
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
TSOP II
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
2
I/O
3
NC
NC
A
4
A
3
A
2
A
5
A
6
A
7
V
SS
V
CC
I/O
5
I/O
4
A
9
A
10
NC
NC
A
8
OE
I/O
7
I/O
6
A
1
A
0
CE
I/O
0
I/O
1
A
11
A
12
NC
NC
NC
18
19
20
21
27
26
25
24
22
23
NC
WE
A
17
NC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1010DV33-10VXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx8 2Mb 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1010DV33-10VXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx8 2Mb 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1010DV33-10ZSXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M FAST ASYNC HI SPD 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1010DV33-10ZSXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M FAST ASYNC HI SPD 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1011BV33-12ZCT | 制造商:Cypress Semiconductor 功能描述: |
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