參數(shù)資料
型號(hào)： CY7C09449PV-AC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 128 Kb Dual-Port SRAM with PCI Bus Controller (PCI-DP)
中文描述： 4K X 32 DUAL-PORT SRAM, 10 ns, PQFP160
封裝： 24 X 24 MM, 1.40 MM HEIGHT, PLASTIC, MO-136BV, TQFP-160
文件頁(yè)數(shù)： 1/50頁(yè)
文件大小： 942K
代理商： CY7C09449PV-AC
128 Kb Dual-Port SRAM with PCI Bus
Controller (PCI-DP)
A primary resource within the CY7C09449PV is its 128 Kb of
dual-port memory. This memory is interfaced to both the PCI
bus and to a local microprocessor bus. This shared memory
can be accessed as a target from both buses at the same time
for inter-process communication. From either the local or PCI
bus the CY7C09449PV can be directed to become a PCI bus
master to move data into or out of the internal shared memory
as a direct memory access (DMA). The CY7C09449PV can
DMA across the PCI bus any number of 32-bit double words
(DWORD), up to 16K bytes. It uses the full bursting capabilities
of the PCI bus for maximum efficiency and can transfer data
over the full 32-bit PCI address space.
The CY7C09449PV implements optional requirements of the
PCI specification by selecting the optimum PCI command for
each transaction it masters to the PCI bus. This maximizes
overall efficiency of the system platform. PCI bridging func-
tions (PCI-to-PCI and Host-to-PCI bridges) use the commands
to enhance prefetch and cache coherency operations. The
CY7C09449PV requests and gains access to the PCI bus as
any master. It does not, within itself, include a PCI bus arbitra-
tion function. Standard PC PCI buses include this function;
embedded systems may need to implement this function.
The CY7C09449PV provides a direct access mechanism from
the local bus to the PCI bus. With it, the local processor can
direct the CY7C09449PV to run a PCI bus master cycle of any
kind to any address. This means that the CY7C09449PV can
run PCI configuration cycles allowing it to be used as a host
bridge.
CY7C09449PV-AC
Cypress Semiconductor Corporation
Document #: 38-06061 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 27, 2002
408-943-2600
09449PV
Features
128 Kb of dual-ported shared memory
Master and Target PCI Specification 2.2 compliant in-
terface
Embedded host bridge capability
Direct interface to many microprocessors
I
O message transport unit; includes four 32-bit, 32-
entry FIFO
Local bus clock rates up to 50 MHz
Single 3.3V Power Supply including compatibility with
3V and 5V PCI Bus signaling
160-pin thin plastic quad flat package
Introduction
The CY7C09449PV is one of the PCI interface controllers in
the
Cypress
Semiconductor
CY7C09449PV provides a PCI master/target interface with di-
rect connections to many popular microprocessors. It provides
128 Kb of dual-port SRAM that is used as shared memory
between the local microprocessor and the PCI bus. An I
2
O
message unit, complete with message queues and interrupt
capability, is also provided. The CY7C09449PV allows the de-
signer to interface an application to the PCI bus in a straight-
forward, inexpensive way.
PCI-DP
family.
The
Functional Overview
The CY7C09449PV is composed of a number of shared re-
sources that allow effective data movement between the local
bus and the PCI bus.
Table of Contents
Features
Introduction
Functional Overview
Pin Configuration
Pin Description
PCI Bus
Local Bus
Timing Diagrams
I
2
C Serial Port and Auto-Configuration
Operations Registers
Performance Characteristics
CY7C09449PV Operations
Ordering Information
Package Diagram
1
1
1
4
5
9
12
16
27
29
41
46
48
48
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