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參數(shù)資料
| 型號： | CY7C09389A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x18 Synchronous Dual Port Static RAM(64K x 18 同步雙端口靜態(tài) RAM) |
| 中文描述： | 64K的x18同步雙端口靜態(tài)存儲器（64K的× 18同步雙端口靜態(tài)RAM）的 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 338K |
| 代理商： | CY7C09389A |
CY7C09269A/79/89
CY7C09369A/79/89
2
PRELIMINARY
Functional Description
The CY7C09269A/79/89 and CY7C09369A/79/89 are high-
speed synchronous CMOS 16K, 32K, and 64K x 16/18 dual-
port static RAMs. Two ports are provided, permitting indepen-
dent, simultaneous access for reads and writes to any location
in memory.
[5]
Registers on control, address, and data lines
allow for minimal set-up and hold times. In pipelined output
mode, data is registered for decreased cycle time. Clock to
data valid t
CD2
= 6.5 ns
[1]
(pipelined). Flow-through mode can
also be used to bypass the pipelined output register to elimi-
nate access latency. In flow-through mode data will be avail-
able
t
CD1
= 15 ns
after the address is clocked into the device.
Pipelined output or flow-through mode is selected via the
FT/PIPE pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
Pin Configurations
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port
’
s burst counter is loaded with the port
’
s Address Strobe
(ADS). When the port
’
s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port
’
s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Notes:
5.
6.
7.
8.
When writing simultaneously to the same location, the final value cannot be guaranteed.
This pin is NC for CY7C09269A.
This pin is NC for CY7C09269A and CY7C09279.
For CY7C09269A and CY7C09279, pin #18 connected to V
CC
is equivalent to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent
to an IDT x16 flow-through device.
1
3
2
92 91 90
84
85
87 86
88
89
83 82 81
76
78 77
79
80
93
94
95
96
97
98
99
100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
72
74
71
A9R
A10R
A11R
A12R
A13R
A14R
UBR
NC
LBR
CE1R
CNTRSTR
OER
FT/PIPER
NC
A15R
GND
R/WR
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
CE0R
58
57
56
55
54
53
52
51
A9L
A10L
A11L
A12L
A13L
A14L
UBL
NC
LBL
CE1L
CNTRSTL
OEL
FT/PIPEL
NC
A15L
VCC
R/WL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
17
18
16
15
9
10
12
11
13
14
8
7
6
4
5
19
20
21
22
23
24
25
A
A
A
A
A
A
C
A
C
G
A
A
A
A
A
C
C
A
A
A
A
A
A
A
A
34 35 36
42
41
39 40
38
37
43 44 45
50
48 49
47
46
N
I
I
I
V
I
I
I
I
G
I
I
I
I
I
I
G
I
I
I
I
V
I
I
I
33
32
31
30
29
28
27
26
100-Pin TQFP (Top View)
[6]
[7]
[6]
[7]
[8]
[8]
CY7C09279 (32K x 16)
CY7C09269A (16K x 16)
CY7C09289 (64K x 16)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C09289V | 3.3V 64K x16 Synchronous Dual Port Static RAM(3.3V 64K x 16 同步雙端口靜態(tài) RAM) |
| CY7C09269V | 3.3V 16K x16 Synchronous Dual Port Static RAM(3.3V 16K x 16 同步雙端口靜態(tài) RAM) |
| CY7C09279V | 3.3V 32K x16 Synchronous Dual Port Static RAM(3.3V 32K x 16 同步雙端口靜態(tài) RAM) |
| CY7C09369V | 3.3V 16Kx18 Synchronous Dual Port Static RAM(3.3V 16K x 18 同步雙端口靜態(tài) RAM) |
| CY7C09379V | 3.3V 32K x18 Synchronous Dual Port Static RAM(3.3V 32K x 18 同步雙端口靜態(tài) RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C09389V-12AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 1.125M-Bit 64K x 18 25ns/12ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:64KX18 3.3V DUAL PORT SRAM - Bulk |
| CY7C09389V-12ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09389V-12AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 3.3V 32Kx18 COM Sync Dual Port 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C09389V-12AXCT | 功能描述:IC SRAM 1.152MBIT 12NS 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C09389V-6AC | 制造商:Rochester Electronics LLC 功能描述:64KX18 3.3V DUAL PORT SRAM - Bulk |
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