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參數(shù)資料
| 型號： | CY7C09379V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 32K x18 Synchronous Dual Port Static RAM(3.3V 32K x 18 同步雙端口靜態(tài) RAM) |
| 中文描述： | 3.3 32K的x18同步雙端口靜態(tài)RAM（3.3 32K的× 18同步雙端口靜態(tài)RAM）的 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 783K |
| 代理商： | CY7C09379V |
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *B
Page 4 of 19
Maximum Ratings
[12]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to V
CC
+0.5V
DC Input Voltage......................................–0.5V to V
CC
+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >1100V
Latch-Up Current......................................................>200mA
Note:
12.The voltage on any input or I/O pin can not exceed the power pin during power-up.
Pin Definitions
Left Port
Right Port
Description
A
0L
–A
15L
ADS
L
A
0R
–A
15R
ADS
R
Address Inputs (A
0
–A
14
for 32K, A
0
–A
13
for 16K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
CE
0L
,CE
1L
CE
0R
,CE
1R
Chip Enable Input. To select either the left or right port, both CE
0
AND CE
1
must be asserted
to their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CLK
L
CNTEN
L
CLK
R
CNTEN
R
CNTRST
L
CNTRST
R
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O
0L
–I/O
17L
LB
L
I/O
0R
–I/O
17R
LB
R
Data Bus Input/Output (I/O
0
–I/O
15
for x16 devices).
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte. (I/O
0
–I/O
8
for x18, I/O
0
–I/O
7
for x16) of the memory array. For read operations both
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
UB
L
OE
L
UB
R
OE
R
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O
8/9L
–I/O
15/17L
).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/W
L
R/W
R
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPE
L
FT/PIPE
R
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
V
CC
Power Input.
Operating Range
Range
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
Commercial
3.3V
±
300 mV
3.3V
±
300 mV
Industrial
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