參數(shù)資料
型號(hào)： CY7C09189
廠商： Cypress Semiconductor Corp.
英文描述： 64K x 9 Synchronous Dual-Port Static RAM(64K x 9 同步雙端口靜態(tài)RAM)
中文描述： 64K的× 9同步雙端口靜態(tài)存儲(chǔ)器（64K的× 9同步雙端口靜態(tài)RAM）的
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 337K
代理商： CY7C09189
CY7C09079/89/99
CY7C09179/89/99
5
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................
–
65
°
C to +150
°
C
Ambient Temperature with Power Applied ..
–
55
°
C to +125
°
C
Supply Voltage to Ground Potential...............
–
0.3V to +7.0V
DC Voltage Applied to
Outputs in High Z State .................................
–
0.5V to +7.0V
DC Input Voltage............................................
–
0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ...........................................>2001V
Latch-Up Current......................................................>200mA
Pin Definitions
Left Port
A
0L
–
A
16L
ADS
L
Right Port
A
0R
–
A
16R
ADS
R
Description
Address Inputs (A
0
A
14
for 32K; A
0
A
15
for 64K; and A
0
A
16
for 128K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
Chip Enable Input. To select either the left or right port, both CE
0
AND CE
1
must be asserted to
their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
0
–
I/O
7
for x8 devices; I/O
0
–
I/O
8
for x9 devices).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
CE
0L
,CE
1L
CE
0R
,CE
1R
CLK
L
CNTEN
L
CLK
R
CNTEN
R
CNTRST
L
CNTRST
R
I/O
0L
–
I/O
8L
OE
L
I/O
0R
–
I/O
8R
OE
R
R/W
L
R/W
R
FT/PIPE
L
FT/PIPE
R
GND
NC
V
CC
Operating Range
Range
Ambient
Temperature
0
°
C to +70
°
C
40
°
C to +85
°
C
V
CC
Commercial
Industrial
5V
±
10%
5V
±
10%
Shaded area contains advance information.
相關(guān)PDF資料
PDF描述
CY7C09199 128K x 9 Synchronous Dual-Port Static RAM(128K x 9 同步雙端口靜態(tài)RAM)
CY7C09289A 64K x16 Synchronous Dual Port Static RAM(64K x 16 同步雙端口靜態(tài) RAM)
CY7C09269A 16K x16 Synchronous Dual Port Static RAM(16K x 16 同步雙端口靜態(tài) RAM)
CY7C09279A 32K x16 Synchronous Dual Port Static RAM(32K x 16 同步雙端口靜態(tài) RAM)
CY7C09369A 16Kx18 Synchronous Dual Port Static RAM(16K x 18 同步雙端口靜態(tài) RAM)
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