參數(shù)資料
型號(hào): CY7C09179V-6AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述: 32K X 9 DUAL-PORT SRAM, 15 ns, PQFP100
封裝: ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件頁(yè)數(shù): 22/28頁(yè)
文件大?。?/td> 657K
代理商: CY7C09179V-6AXC
CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 3 of 28
Functional Description
The CY7C09089V/99V and CY7C09179V/99V are high speed
synchronous CMOS 64 K/128 K × 8 and 32 K/128 K × 9 dual-port
static RAMs. Two ports are provided, permitting independent,
simultaneous access for reads and writes to any location in
memory.[4] Registers on control, address, and data lines enable
minimal setup and hold times. In pipelined output mode, data is
registered for decreased cycle time. Clock to data valid
tCD2 =6.5 ns[5] (pipelined). Flow-through mode can also be used
to bypass the pipelined output register to eliminate access
latency. In flow-through mode, data is available tCD1 = 18 ns after
the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the
LOW-to-HIGH transition of the clock signal. The internal write
pulse is self-timed to enable the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE0 LOW and CE1 HIGH to reactivate
the outputs.
Counter enable inputs are provided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW-to-HIGH transition of
that port’s clock signal. This reads/writes one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and loops
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Notes
4. When writing simultaneously to the same location, the final value cannot be guaranteed.
5. See page 9 and page 10 for Load Conditions.
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