參數(shù)資料
型號: CY7C09159AV-12AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM
中文描述: 8K X 9 DUAL-PORT SRAM, 25 ns, PQFP100
封裝: PLASTIC, LEAD FREE, TQFP-100
文件頁數(shù): 6/16頁
文件大?。?/td> 526K
代理商: CY7C09159AV-12AXC
CY7C09159AV
CY7C09169AV
Document #: 38-06053 Rev. *B
Page 14 of 16
Notes:
25. “X” = “don’t care,” “H” = VIH, “L” = VIL.
26. ADS, CNTEN, CNTRST = “don’t care.”
27. OE is an asynchronous input signal.
28. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
29. CE0 and OE = VIL; CE1 and R/W = VIH.
30. Data shown for Flow-through mode; pipelined mode output will be delayed by one cycle.
31. Counter operation is independent of CE0 and CE1.
Read/Write and Enable Operation[25, 26, 27]
Inputs
Outputs
OE
CLK
CE0
CE1
R/W
I/O0–I/O9
Operation
X
H
X
High-Z
Deselected[28]
X
L
X
High-Z
Deselected[28]
X
L
H
L
DIN
Write
L
H
DOUT
Read[28]
H
X
L
H
X
High-Z
Outputs Disabled
Address Counter Control Operation[25, 29, 30, 31]
Address
Previous
Address
CLK
ADS
CNTEN CNTRST
I/O
Mode
Operation
X
L
Dout(0)
Reset
Counter Reset to Address 0
An
X
L
X
H
Dout(n)
Load
Address Load into Counter
X
An
H
Dout(n)
Hold
External Address Blocked—Counter
Disabled
X
An
H
L
H
Dout(n+1)
Increment
Counter Enabled—Internal Address
Generation
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