參數(shù)資料
型號: CY7C09099V-7AXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述: 128K X 8 DUAL-PORT SRAM, 18 ns, PQFP100
封裝: ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件頁數(shù): 15/28頁
文件大?。?/td> 657K
代理商: CY7C09099V-7AXI
CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 22 of 28
Figure 17. Counter Reset (Pipelined Outputs)[54, 55, 56, 57]
Switching Waveforms (continued)
tCH2
tCL2
tCYC2
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT
Q0
Q1
Qn
D0
AX
01
An
An+1
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tSD
tHD
tSW tHW
An
An+1
tSA
tHA
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Notes
54. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
55. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
56. CE0 = VIL; CE1 = VIH.
57. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
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