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參數(shù)資料
| 型號： | CY7C09089V-12AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM |
| 中文描述： | 64K X 8 DUAL-PORT SRAM, 25 ns, PQFP100 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 599K |
| 代理商： | CY7C09089V-12AXC |
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *E
Page 4 of 20
Notes
8. This pin is NC for CY7C09179V.
9. This pin is NC for CY7C09179V and CY7C09189V
Selection Guide
Description
CY7C09079V/89V/99V
CY7C09179V/89V/99V-6[1]
CY7C09079V/89V/99V
CY7C09179V/89V/99V-7[1]
CY7C09079V/89V/99V
CY7C09179V/89V/99V
-9
CY7C09079V/89V/99V
CY7C09179V/89V/99V
-12
fMAX2 (MHz)
(Pipelined)
100
83
67
50
Max. Access Time
(ns) (Clock to Data,
Pipelined)
6.5
7.5
9
12
Typical Operating
Current ICC (mA)
175
155
135
115
Typical Standby
Current for ISB1
(mA) (Both Ports
TTL Level)
25
20
Typical Standby
Current for ISB3
(
A) (Both Ports
CMOS Level)
10
A
10
A10 A
10
A
Pin Definitions
Left Port
Right Port
Description
A0L–A16L
A0R–A16R
Address Inputs (A0–A14 for 32K; A0–A15 for 64K; and A0–A16 for 128K devices).
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads
the burst counter with the address present on the address pins.
CE0L,CE1L
CE0R,CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
to their active states (CE0 VIL and CE1 VIH).
CLKL
CLKR
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are
asserted LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O8L
I/O0R–I/O8R
Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices).
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during
read operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
VCC
Power Input.
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| CY7C09089V-12AXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 64Kx8 12ns 512Kb SYNC DUAL PORT 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C09089V-6AXC | 功能描述:IC SRAM 512KBIT 6.5NS 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C09089V-7AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 512K-Bit 64K x 8 18ns/7.5ns 100-Pin TQFP |
| CY7C09099V-12AC | 功能描述:IC SRAM 1MBIT 12NS 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C09099V-12AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 3.3V 128Kx8 COM Sync Dual Port 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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