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參數(shù)資料
| 型號(hào)： | CY7C09089 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 8 Synchronous Dual-Port Static RAM(64K x 8 同步雙端口靜態(tài)RAM) |
| 中文描述： | 64KX8的同步雙端口靜態(tài)存儲(chǔ)器（64KX8的同步雙端口靜態(tài)RAM）的 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 337K |
| 代理商： | CY7C09089 |
CY7C09079/89/99
CY7C09179/89/99
2
PRELIMINARY
Functional Description
The CY7C09079/89/99 and CY7C09179/89/99 are high-
speed synchronous CMOS 32K, 64K, and 128K x 8/9 dual-
port static RAMs. Two ports are provided, permitting indepen-
dent, simultaneous access for reads and writes to any location
in memory.
[4]
Registers on control, address, and data lines
allow for minimal set-up and hold times. In pipelined output
mode, data is registered for decreased cycle time. Clock to
data valid t
CD2
= 6.5 ns
[1]
(pipelined). Flow-through mode can
also be used to bypass the pipelined output register to elimi-
nate access latency. In flow-through mode data will be avail-
able
t
CD1
= 15 ns
after the address is clocked into the device.
Pipelined output or flow-through mode is selected via the
FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port
’
s burst counter is loaded with the port
’
s Address Strobe
(ADS). When the port
’
s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port
’
s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
4.
When writing simultaneously to the same location, the final value cannot be guaranteed.
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| CY7C09089V-12AC | 功能描述:IC SRAM 512KBIT 12NS 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
| CY7C09089V-12AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3V 64Kx8 COM Sync Dual Port 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C09089V-12AXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 64Kx8 12ns 512Kb SYNC DUAL PORT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C09089V-6AXC | 功能描述:IC SRAM 512KBIT 6.5NS 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C09089V-7AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 512K-Bit 64K x 8 18ns/7.5ns 100-Pin TQFP |
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