參數(shù)資料
型號(hào): CY7C0853V-100BBI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: 256K X 36 DUAL-PORT SRAM, 5 ns, PBGA172
封裝: 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, FBGA-172
文件頁(yè)數(shù): 23/29頁(yè)
文件大小: 764K
代理商: CY7C0853V-100BBI
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
Document #: 38-06070 Rev. *D
Page 23 of 29
Left_Port (L_Port) Write to Right_Port (R_Port) Read
[38, 39, 40]
Notes:
38. CE
= OE = ADS = CNTEN = B0 – B3 = LOW; CE
= CNTRST = MRST = CNT/MSK = HIGH.
39. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
CCS
is violated, indeterminate data will be Read out.
40. If t
CCS
< minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * t
CYC2
+ t
) after the rising edge of R_Port's clock.
If t
CCS
> minimum specified value, then R_Port will Read the most recent data (written by L_Port) (t
CYC2
+ t
CD2
) after the rising edge of R_Port's clock.
Switching Waveforms
(continued)
t
SA
t
HA
t
SW
t
HW
t
CH2
t
CL2
t
CYC2
CLK
L
R/W
L
A
n
D
n
t
CKHZ
t
HD
t
SA
A
n
t
HA
Q
n
t
DC
t
CCS
t
SD
t
CKLZ
t
CH2
t
CL2
t
CYC2
t
CD2
L_PORT
ADDRESS
L_PORT
DATA
IN
CLK
R
R/W
R
R_PORT
ADDRESS
R_PORT
DATA
OUT
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