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參數(shù)資料
| 型號： | CY7C0852V-133BBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| 中文描述： | 128K X 36 DUAL-PORT SRAM, 4.4 ns, PBGA172 |
| 封裝： | 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, FBGA-172 |
| 文件頁數(shù)： | 18/29頁 |
| 文件大小： | 764K |
| 代理商： | CY7C0852V-133BBC |
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CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
Document #: 38-06070 Rev. *D
Page 18 of 29
Bank Select Read
[26, 27]
Read-to-Write-to-Read (OE = LOW)
[25, 28, 29, 30, 31]
Notes:
26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0852V device from this data
sheet. ADDRESS
(B1)
= ADDRESS
(B2)
.
27. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
29. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
30.
CE
0
= OE = B0 – B3 = LOW; CE
1
= R/W = CNTRST = MRST = HIGH.
31. CE
= B0 – B3 = R/W = LOW; CE
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Switching Waveforms
(continued)
Q
3
Q
1
Q
0
Q
2
A
0
A
1
A
2
A
3
A
4
A
5
Q
4
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
t
SC
t
HC
t
SA
t
HA
t
SC
t
HC
t
SC
t
HC
t
SC
t
HC
t
CKHZ
t
DC
t
DC
t
CD2
t
CKLZ
t
CD2
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CH2
t
CL2
t
CYC2
CLK
ADDRESS
(B1)
CE
(B1)
DATA
OUT(B2)
DATA
OUT(B1)
ADDRESS
(B2)
CE
(B2)
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
t
HW
t
SW
t
CD2
t
CKHZ
t
SD
t
HD
t
CKLZ
READ
t
CD2
NO
OPERATION
WRITE
READ
CLK
CE
R/W
ADDRESS
DATA
IN
DATA
OUT
A
n
A
n+1
A
n+2
A
n+2
D
n+2
A
n+3
A
n+4
Q
n
Q
n+3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C0852V-133BBI | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0852V-167AC | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0852V-167BBC | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0853V-100BBC | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C0852V-133BBCT | 功能描述:靜態(tài)隨機存取存儲器 3.3V 128Kx36 COM Sync Dual Port 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C0852V-133BBI | 功能描述:靜態(tài)隨機存取存儲器 4MB (128Kx36) 3.3v 133MHz Synch 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C0852V-150BBC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C0852V-167AXC | 功能描述:IC SRAM 4MBIT 167MHZ 176LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C0852V-167BBC | 功能描述:靜態(tài)隨機存取存儲器 4MB (128Kx36) 3.3v 167MHz Sync 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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