參數(shù)資料
型號(hào): CY7C0852AV-167AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): SRAM
英文描述: FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: 128K X 36 DUAL-PORT SRAM, 4 ns, PQFP176
封裝: 24 X 24 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-176
文件頁(yè)數(shù): 6/36頁(yè)
文件大小: 956K
代理商: CY7C0852AV-167AXC
CY7C0850AV,CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document #: 38-06070 Rev. *J
Page 14 of 36
Maximum Ratings
Exceeding maximum ratings[19] may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature............................... –65
C to + 150 C
Ambient temperature with
Power applied.......................................... –55
C to + 125 C
Supply voltage to ground potential ..............–0.5 V to + 4.6 V
DC voltage applied to
Outputs in High-Z state........................ –0.5 V to VDD + 0.5 V
DC input voltage ............................. –0.5 V to VDD + 0.5 V[20]
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage........................................... > 2000 V
(JEDEC JESD22-A114-2000B)
Latch-up current ..................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VDD
Commercial
0
C to +70 C
3.3 V ± 165 mV
Industrial
–40
C to +85 C
3.3 V ± 165 mV
Electrical Characteristics
Over the Operating Range
Parameter
Description
-167
-133
-100
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOH
Output HIGH voltage (VDD = Min., IOH= –4.0 mA)
2.4
2.4
2.4
V
VOL
Output LOW voltage (VDD = Min., IOL= +4.0 mA)
0.4
0.4
V
VIH
Input HIGH voltage
2.0
2.0
2.0
V
VIL
Input LOW voltage
0.8
0.8
V
IOZ
Output leakage current
–10
10
–10
10
–10
10
A
IIX1
Input leakage current except TDI, TMS, MRST
–10
10
–10
10
–10
10
A
IIX2
Input leakage current TDI, TMS, MRST
–0.1
1.0
–0.1
1.0
–0.1
1.0
mA
ICC
Operating current for
(VDD = Max.,IOUT = 0 mA),
Outputs disabled
CY7C0850AV
CY7C0851V/AV
CY7C0852V/AV
225
300
225
300
mA
CY7C0853V/
CY7C0853AV
270
400
200
310
ISB1[22]
Standby current (both ports TTL level)
CEL and CER VIH, f = fMAX
90
115
90
115
90
115
mA
ISB2[22]
Standby current (one port TTL level)
CEL | CER VIH, f = fMAX
160
210
160
210
160
210
mA
ISB3[22]
Standby current (both ports CMOS level)
CEL and CER VDD – 0.2 V, f = 0
55
75
55
75
55
75
mA
ISB4[22]
Standby current (one port CMOS level)
CEL | CER VIH, f = fMAX
160
210
160
210
160
210
mA
ISB5
Operating current
(VDD = Max, IOUT = 0 mA, f = 0)
Outputs disabled
CY7C0853V/
CY7C0853AV
70
100
70
100
mA
Capacitance
Part Number[21]
Parameter
Description
Test Conditions
Max
Unit
CY7C0850AV,CY7C0851V
CY7C0851AV, CY7C0852V,
CY7C0852AV
CIN
Input capacitance
TA = 25 C, f = 1 MHz,
VDD = 3.3 V
13
pF
COUT
Output capacitance
10
pF
CY7C0853V,CY7C0853AV
CIN
Input capacitance
22
pF
COUT
Output capacitance
20
pF
Notes
19. The voltage on any input or I/O pin can not exceed the power pin during power up.
20. Pulse width < 20 ns.
21. COUT also references CI/O.
22. ISB1, ISB2, ISB3 and ISB4 are not applicable forCY7C0853V/ CY7C0853AV because it can not be powered down by using chip enable pins.
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