參數(shù)資料
型號(hào)： CY7C0851V-167AC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： CONNECTOR ACCESSORY
中文描述： 64K X 36 DUAL-PORT SRAM, 4 ns, PQFP176
封裝： 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
文件頁(yè)數(shù)： 7/29頁(yè)
文件大?。?/td> 764K
代理商： CY7C0851V-167AC
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
Document #: 38-06070 Rev. *D
Page 7 of 29
Master Reset
The FLEx36 family devices undergo a complete reset by
taking its MRST input LOW. The MRST input can switch
asynchronously to the clocks. The MRST initializes the
internal burst counters to zero, and the counter mask registers
to all ones (completely unmasked). The MRST also forces the
Mailbox Interrupt (INT) flags and the Counter Interrupt
(CNTINT) flags HIGH. The MRST must be performed on the
FLEx36 family devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports.
Table 2
shows the interrupt operation for both ports of CY7C0853V.
The highest memory location, 3FFFF is the mailbox for the
right port and 3FFFE is the mailbox for the left port.
Table 2
shows that in order to set the INT
R
flag, a Write operation by
the left port to address 3FFFF will assert INT
R
LOW. At least
one byte has to be active for a Write to generate an interrupt.
A valid Read of the 3FFFF location by the right port will reset
INT
R
HIGH. At least one byte has to be active in order for a
Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to
is asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the contents of the mailbox. The interrupt flag
is set in a flow-thru mode (i.e., it follows the clock edge of the
writing port). Also, the flag is reset in a flow-thru mode (i.e., it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Table 2. Interrupt Operation Example
[1, 4, 5, 6, 7]
Function
Left Port
Right Port
R/W
L
L
X
X
H
CE
L
L
X
X
L
A
0
L
–17
L
3FFFF
X
X
3FFFE
INT
L
X
X
L
H
R/W
R
X
H
L
X
CE
R
X
L
L
X
A
0R–17R
X
3FFFF
3FFFE
X
INT
R
L
H
X
X
Set Right INT
R
Flag
Reset Right INT
R
Flag
Set Left INT
L
Flag
Reset Left INT
L
Flag
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)
[8, 9]
CLK
MRST
CNT/MSK
CNTRST
ADS
X
L
X
X
X
CNTEN
X
Operation
Master Reset
Description
Reset address counter to all 0s and mask
register to all 1s.
Reset counter unmasked portion to all 0s.
H
H
L
X
X
Counter Reset
H
H
H
L
L
Counter Load
Load counter with external address value
presented on address lines.
Counter Readback Read out counter internal value on
address lines.
Counter Increment Internally increment address counter
value.
Counter Hold
Constantly hold the address value for
multiple clock cycles.
Mask Reset
Reset mask register to all 1s.
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
L
X
X
H
L
H
L
L
Mask Load
Load mask register with value presented
on the address lines.
Read out mask register value on address
lines.
Operation undefined
H
L
H
L
H
Mask Readback
H
L
H
H
X
Reserved
Notes:
4.
CE is internal signal. CE = LOW if CE
= LOW and CE
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the
CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
OE is “Don’t Care” for mailbox operation.
At least one of B0, B1, B2, or B3 must be LOW.
A16x is a NC for CY7C0851V, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850V, therefore the Interrupt Addresses
are 7FFF and 6FFF.
“X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
Counter operation and mask register operation is independent of chip enables.
5.
6.
7.
8.
9.
相關(guān)PDF資料
PDF描述
CY7C0851V-167BBC CONNECTOR ACCESSORY
CY7C0853V-133BBC FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853V-133BBI FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853V FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0852V-133AC FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C0851V-167AXC 功能描述:IC SRAM 2MBIT 167MHZ 176LQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2
CY7C0851V-167BBC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2MB (64Kx36) 3.3v 167MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C0852AV-133AC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 128KX36 4.7NS 176TQFP - Trays
CY7C0852AV-133ACT 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 128KX36 4.7NS 176TQFP - Tape and Reel
CY7C0852AV-133AI 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 128KX36 4NS 176TQFP - Bulk
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