參數(shù)資料
型號： CY7C0850V
廠商： Cypress Semiconductor Corp.
英文描述： FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述： FLEx36TM 3.3 32K/64K/128K/256K × 36同步雙口RAM
文件頁數(shù)： 11/29頁
文件大?。?/td> 764K
代理商： CY7C0850V
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
Document #: 38-06070 Rev. *D
Page 11 of 29
IEEE 1149.1 Serial Boundary Scan (JTAG)
[13]
The
incorporates an IEEE 1149.1 serial boundary scan test access
port (TAP). The TAP controller functions in a manner that does
not conflict with the operation of other devices using
1149.1-compliant
TAPs.
The
JEDEC-standard 3.3V I/O logic levels. It is composed of three
input connections and one output connection required by the
test logic defined by the standard.
CY7C0850V/CY7C0851V/CY7C0852V/CY7C0853V
TAP
operates
using
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (V
DD
) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the devices are
operating. An MRST must be performed on the devices after
power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the devices in a scan
test. Therefore the tester should be configured to never enter
the PAUSE-DR state.
.
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
H
H
L
H
1
1
0s
1
0
1
0
1
0
1
0
0
Xs
1
X
0
X
0
X
0
1
1
Xs
1
X
1
X
1
X
1
0
0
Xs
1
X
0
X
0
X
0
Masked Address
Unmasked Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
Figure 2. Programmable Counter-Mask Register Operation
[1, 12]
Table 4. Identification Register Definitions
Instruction Field
Revision Number (31:28)
Cypress Device ID
(27:12)
Value
Description
0h
C001h
C002h
C092h
034h
1
Reserved for version number.
Defines Cypress part number for the CY7C0851V
Defines Cypress part number for the CY7C0852V and CY7C0853V
Defines Cypress part number for the CY7C0850V
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Notes:
12. The “X” in this diagram represents the counter upper bits.
13. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance
相關(guān)PDF資料
PDF描述
CY7C0850V-133AC FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0850V-133AI FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0850V-133BBC FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0850V-133BBI FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0850V-167AC FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C0850V-133AC 功能描述:靜態(tài)隨機(jī)存取存儲器 1M COM Sync DualPort RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C0850V-133AI 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 1.125MBIT 32KX36 4NS 176TQFP - Bulk
CY7C0850V-133BBC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 1.125MBIT 32KX36 4.4NS 172BGA - Bulk
CY7C0850V-133BBI 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 1.125MBIT 32KX36 4NS 172BGA - Bulk
CY7C0850V-167AC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 1.125MBIT 32KX36 4NS 176TQFP - Bulk
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