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參數(shù)資料
| 型號： | CY7C0850V-133AI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| 中文描述： | 32K X 36 DUAL-PORT SRAM, 4.4 ns, PQFP176 |
| 封裝： | 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176 |
| 文件頁數(shù)： | 18/29頁 |
| 文件大?。?/td> | 764K |
| 代理商： | CY7C0850V-133AI |
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CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
Document #: 38-06070 Rev. *D
Page 18 of 29
Bank Select Read
[26, 27]
Read-to-Write-to-Read (OE = LOW)
[25, 28, 29, 30, 31]
Notes:
26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0852V device from this data
sheet. ADDRESS
(B1)
= ADDRESS
(B2)
.
27. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
29. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
30.
CE
0
= OE = B0 – B3 = LOW; CE
1
= R/W = CNTRST = MRST = HIGH.
31. CE
= B0 – B3 = R/W = LOW; CE
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Switching Waveforms
(continued)
Q
3
Q
1
Q
0
Q
2
A
0
A
1
A
2
A
3
A
4
A
5
Q
4
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
t
SC
t
HC
t
SA
t
HA
t
SC
t
HC
t
SC
t
HC
t
SC
t
HC
t
CKHZ
t
DC
t
DC
t
CD2
t
CKLZ
t
CD2
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CH2
t
CL2
t
CYC2
CLK
ADDRESS
(B1)
CE
(B1)
DATA
OUT(B2)
DATA
OUT(B1)
ADDRESS
(B2)
CE
(B2)
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
t
HW
t
SW
t
CD2
t
CKHZ
t
SD
t
HD
t
CKLZ
READ
t
CD2
NO
OPERATION
WRITE
READ
CLK
CE
R/W
ADDRESS
DATA
IN
DATA
OUT
A
n
A
n+1
A
n+2
A
n+2
D
n+2
A
n+3
A
n+4
Q
n
Q
n+3
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C0850V-133BBC | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V-133BBI | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V-167AC | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V-167BBC | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851V-133AC | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C0850V-133BBC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 1.125MBIT 32KX36 4.4NS 172BGA - Bulk |
| CY7C0850V-133BBI | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 1.125MBIT 32KX36 4NS 172BGA - Bulk |
| CY7C0850V-167AC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 1.125MBIT 32KX36 4NS 176TQFP - Bulk |
| CY7C0850V-167BBC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 1.125MBIT 32KX36 4NS 172BGA - Bulk |
| CY7C0851AV-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 2.25MBIT 64KX36 4.7NS 176TQFP - Trays |
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