參數(shù)資料
型號(hào): CY7C056V-10BAC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 3.3V 16K/32K x 36 FLEx36⑩ Asynchronous Dual-Port Static RAM
中文描述: 16K X 36 DUAL-PORT SRAM, 10 ns, PBGA172
封裝: 15 X 15 MM, 0.51 MM HEIGHT, 1 MM PITCH, BGA-172
文件頁(yè)數(shù): 1/22頁(yè)
文件大小: 280K
代理商: CY7C056V-10BAC
3.3V 16K/32K x 36
FLEx36 Asynchronous Dual-Port Static RAM
CY7C056V
CY7C057V
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
April 27, 2000
1
Features
True dual-ported memory cells which allow simulta-
neous access of the same memory location
16K x 36 organization (CY7C056V)
32K x 36 organization (CY7C057V)
0.25-micron CMOS for optimum speed/power
High-speed access: 10/12/15/20 ns
Low operating power
Active: I
CC
= 260 mA (typical)
—Standby: I
SB3
= 10
μ
A (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 72 bits or more using Mas-
ter/Slave Chip Select when using more than one device
On-Chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Byte Select on Left Port
Bus Matching on Right Port
Depth Expansion via dual chip enables
Pin select for Master or Slave
Commercial and Industrial Temperature Ranges
Compact package
—144-Pin TQFP (20 x 20 x 1.4 mm)
172-Ball BGA (1.0 mm pitch) (15 x 15 x .51 mm)
Notes:
1.
2.
A
–A
for 16K; A
–A
for 32K devices.
BUSY is an output in Master mode and an input in Slave mode.
R/W
L
B
0
–B
3
CE
0L
CE
1L
OE
L
I/O
Control
Address
Decode
BUSY
L
INT
L
CE
L
Interrupt
Semaphore
Arbitration
SEM
L
M/S
R/W
R
CE
0R
CE
1R
OE
R
BA
WA
CE
R
Logic Block Diagram
A
0L
–A
13/14L
True Dual-Ported
RAM Array
BUSY
R
INT
R
SEM
R
Address
Decode
A
0R
–A
13/14R
[2]
[2]
[1]
[1]
14/15
14/15
14/15
14/15
Left
Port
Control
Logic
I/O
18L
–I/O
26L
9
I/O
27L
–I/O
35L
9
I/O
0L
–I/O
8L
9
I/O
9L
–I/O
17L
9
Right
Port
Control
Logic
I/O
Control
9
9
I/O
R
9
9
Bus
Match
9/18/36
BM
SIZE
For the most recent information, visit the Cypress web site at www.cypress.com
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