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參數(shù)資料
| 型號： | CY7C038V-25AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 32K/64K x 16/18 Dual-Port Static RAM |
| 中文描述： | 64K X 18 DUAL-PORT SRAM, 25 ns, PQFP100 |
| 封裝： | LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大小： | 236K |
| 代理商： | CY7C038V-25AXC |
3.3V 32K/64K x 16/18 Dual-Port Static RAM
CY7C027V/028V
CY7C037V/038V
Pb
LEAD-FREE
Cypress Semiconductor Corporation
Document #: 38-06078 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised September 20, 2004
Features
True Dual-Ported memory cells which allow
simultaneous access of the same memory location
32K x 16 organization (CY7C027V)
64K x 16 organization (CY7C028V)
32K x 18 organization (CY7C037V)
64K x 18 organization (CY7C038V)
0.35-micron CMOS for optimum speed/power
High-speed access: 15/20/25 ns
Low operating power
—
Active: I
CC
= 115 mA (typical)
—Standby: I
SB3
= 10
μ
A (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Separate upper-byte and lower-byte control
Dual Chip Enables
Pin select for Master or Slave
Commercial and Industrial temperature ranges
100-pin Lead(Pb)-free TQFP and 100-pin TQFP
Notes:
1.
2.
3.
4.
I/O
8
–I/O
15
for x16 devices; I/O
–I/O
for x18 devices.
I/O
–I/O
for x16 devices; I/O
–I/O
for x18 devices.
A
–A
for 32K; A
–A
for 64K devices.
BUSY is an output in master mode and an input in slave mode.
R/W
L
UB
L
CE
0L
CE
1L
OE
L
I/O
8/9L
–I/O
15/17L
I/O
Control
Address
Decode
A
0L
–A
14/15L
CE
L
OE
L
R/W
L
SEM
L
BUSY
L
INT
L
UB
L
LB
L
I/O
Control
CE
L
Interrupt
Semaphore
Arbitration
M/S
LB
L
I/O
0L
–I/O
7/8L
R/W
R
UB
R
CE
0R
CE
1R
OE
R
I/O
8/9L
–I/O
15/17R
CE
R
LB
R
I/O
0L
–I/O
7/8R
Logic Block Diagram
A
0L
–A
14/15L
True Dual-Ported
RAM Array
A
0R
–A
14/15R
CE
R
OE
R
R/W
R
SEM
R
BUSY
R
INT
R
UB
R
LB
R
Address
Decode
A
0R
–A
14/15R
[1]
[1]
[2]
[2]
[3]
[4]
[4]
[3]
15/16
8/9
8/9
15/16
8/9
8/9
15/16
15/16
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