參數(shù)資料
型號(hào): CY7C025AV-25AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
中文描述: 8K X 16 DUAL-PORT SRAM, 25 ns, PQFP100
封裝: PLASTIC, MS-026, TQFP-100
文件頁數(shù): 9/19頁
文件大?。?/td> 241K
代理商: CY7C025AV-25AC
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *E
Page 9 of 19
AC Test Loads and Waveforms
3.0V
GND
90%
90%
10%
3 ns
3 ns
10%
ALL INPUTPULSES
(a) Normal Load (Load 1)
R1 = 590
3.3V
OUTPUT
R2 = 435
C = 30 pF
V
TH
= 1.4V
OUTPUT
C = 30pF
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
(Used for t
LZ
, t
HZ
, t
HZWE
, and t
LZWE
R1 = 590
R2 = 435
3.3V
OUTPUT
C = 5 pF
R
TH
= 250
including scope and jig)
Switching Characteristics
Over the Operating Range
[18]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE[19]
t
DOE
t
LZOE[20, 21, 22]
t
HZOE[20, 21, 22]
t
LZCE[20, 21, 22]
t
HZCE[20, 21, 22]
t
PU[22]
t
PD[22]
t
ABE[19]
Write Cycle
t
WC
t
SCE[19]
t
AW
t
HA
t
SA[19]
t
PWE
t
SD
Notes:
18. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
19. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
20. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
21. Test conditions used are Load 3.
22. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing
with Busy waveform.
Description
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
Min.
Max.
Unit
-25
Min.
Max.
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
20
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
3
3
20
12
25
13
3
3
12
15
3
3
12
15
0
0
20
20
25
25
Write Cycle Time
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-up to Write Start
Write Pulse Width
Data Set-up to Write End
20
15
15
0
0
15
15
25
20
20
0
0
20
15
ns
ns
ns
ns
ns
ns
ns
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