參數(shù)資料
型號: CY7C018-20AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 64K/128K x 8/9 Dual-Port Static RAM
中文描述: 64K X 9 DUAL-PORT SRAM, 20 ns, PQFP100
封裝: PLASTIC, TQFP-100
文件頁數(shù): 1/19頁
文件大?。?/td> 537K
代理商: CY7C018-20AC
64K/128K x 8/9 Dual-Port Static RAM
CY7C008/009
CY7C018/019
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-06041 Rev. *C
Revised June 22, 2004
Features
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
64K x 8 organization (CY7C008)
128K x 8 organization (CY7C009)
64K x 9 organization (CY7C018)
128K x 9 organization (CY7C019)
0.35-micron CMOS for optimum speed/power
High-speed access: 12
[1]
/15/20 ns
Low operating power
Active: I
CC
= 180 mA (typical)
—Standby: I
SB3
= 0.05 mA (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flags for port-to-port communication
Dual Chip Enables
Pin select for Master or Slave
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
Notes:
1.
2.
3.
4.
See page 6 for Load Conditions.
I/O
0
–I/O
for x8 devices; I/O
0
–I/O
for x9 devices.
A
–A
for 64K devices; A
–A
for 128K.
BUSY is an output in master mode and an input in slave mode.
I/O
Control
Address
Decode
A
0L
–A
15/16L
CE
L
OE
L
R/W
L
SEM
L
BUSY
L
INT
L
I/O
Control
Interrupt
Semaphore
Arbitration
M/S
Logic Block Diagram
A
0L
–A
15/16L
True Dual-Ported
RAM Array
A
0R
–A
15/16R
CE
R
OE
R
R/W
R
SEM
R
BUSY
R
INT
R
Address
Decode
A
0R
–A
15/16R
[2]
[2]
[3]
[4]
[4]
[3]
R/W
L
CE
0L
CE
1L
OE
L
I/O
0L
–I/O
7/8L
CE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0R
–I/O
7/8R
CE
R
16/17
8/9
16/17
8/9
16/17
16/17
CY7C008/009
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