參數(shù)資料
型號(hào): CY7C017AV-20JC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
中文描述: 32K X 9 DUAL-PORT SRAM, 20 ns, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 8/20頁(yè)
文件大小: 301K
代理商: CY7C017AV-20JC
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 8 of 20
Data Retention Mode
The CY7C0138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data reten-
tion:
1. Chip enable (CE) must be held HIGH during data retention, with-
in V
CC
to V
CC
0.2V.
2. CE must be kept between V
CC
0.2V and 70% of V
CC
during the power-up and power-down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the
minimum operating voltage (3.0 volts).
Notes:
22. t
is a calculated parameter and is the greater of t
t
(actual) or t
t
(actual).
23.
CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25
°
C. This parameter is guaranteed but not tested.
t
WB
t
WH
t
BDD[22]
INTERRUPT TIMING
[21]
t
INS
t
INR
SEMAPHORE TIMING
t
SOP
t
SWRD
t
SPS
t
SAA
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
0
0
17
ns
ns
ns
15
20
25
INT Set Time
INT Reset Time
20
20
20
20
ns
ns
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
5
12
5
5
ns
ns
ns
ns
20
25
Switching Characteristics
Over the Operating Range
[15]
(continued)
Parameter
Description
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
Min.
Max.
Unit
-25
Min.
Max.
Timing
Parameter
Test Conditions
[23]
Max.
Unit
ICC
DR1
@ VCC
DR
= 2V
50
μ
A
Data Retention Mode
3.0V
3.0V
V
CC
>
2.0V
V
CC
to V
CC
0.2V
V
CC
CE
t
RC
VIH
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CY7C017AV-25JC 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C018 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:64K/128K x 8/9 Dual-Port Static RAM
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