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參數(shù)資料
| 型號： | CY7B9950 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer(2.5/3.3V, 200MHz，高速，多相PLL時鐘緩沖器) |
| 中文描述： | 2.5/3.3V，200 MHz高速多相PLL時鐘緩沖器（2.5/3.3V，200MHz的，高速，多相鎖相環(huán)時鐘緩沖器） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 278K |
| 代理商： | CY7B9950 |
2.5/3.3V, 200-MHz High-Speed Multi-Phase
PLL Clock Buffer
RoboClock
CY7B9950
Cypress Semiconductor Corporation
Document #: 38-07338 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised March 15, 2006
Features
2.5V or 3.3V operation
Split output bank power supplies
Output frequency range: 6 MHz to 200 MHz
50 ps typical matched-pair Output-output skew
50 ps typical Cycle-cycle jitter
49.5/50.5% typical output duty cycle
Selectable output drive strength
Selectable positive or negative edge synchronization
Eight LVTTL outputs driving 50
terminated lines
LVCMOS/LVTTL over-voltage-tolerant reference input
Phase adjustments in 625-/1250-ps steps up to +7.5 ns
2x, 4x multiply and (1/2)x, (1/4)x divide ratios
Spread-Spectrum-compatible
Industrial temp. range: –40
°
C to +85
°
C
32-pin TQFP package
Description
The CY7B9950 RoboClock
is a low-voltage, low-power,
eight-output, 200-MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance computer and communication systems.
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature allows the user to
skew the outputs to lead or lag the reference clock. Any one
of the outputs can be connected to feedback input to achieve
different reference frequency multiplication and divide ratios
and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin
controls the synchronization of the output signals to either the
rising or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA(3.3V).
Block Diagram
Pin Configuration
PE/HD
TEST
FS
3
3
REF
FB
2F1:0
1F1:0
3F1:0
4F1:0
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
4Q0
4Q1
PLL
3
3
3
3
3
3
3
3
Phase
Select
Phase
Select
Phase
Select
and /K
Phase
Select
and /M
3
sOE#
VDDQ1
VDDQ4
VDDQ3
1Q0
1Q1
VSS
VSS
3
F
V
R
V
T
2
2
CY7B9950
1
2
3
4
5
6
7
8
3F1
4F0
4F1
4Q0
VSS
4Q1
V
3
3
V
2
F
V
2
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
1F0
sOE#
VDDQ1
PE/HD
VDDQ4
1F1
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PDF描述 |
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| CY7C008V-15AC | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:55; Connector Shell Size:23; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
| CY7C019V-15AC | 3.3V 64K/128K x 8/9 Dual-Port Static RAM |
| CY7C008V-20AC | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:55; Connector Shell Size:23; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
| CY7C008V-25AC | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:55; Connector Shell Size:23; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B9950_06 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer |
| CY7B9950_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer |
| CY7B9950AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7B9950ACT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer |
| CY7B9950AI | 制造商:Rochester Electronics LLC 功能描述:2.5V/3.3V 200 MHZ PROGRAMMABLE SKEW CLOCK BUFFER IND TEMP - Bulk |
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