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參數(shù)資料
| 型號(hào)： | CY7B9910-7SI[20] |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | Low Skew Clock Buffer |
| 中文描述： | 低偏移時(shí)鐘緩沖器 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 281K |
| 代理商： | CY7B9910-7SI[20] |
CY7B9910
CY7B9920
Document Number: 38-07135 Rev. *B
Page 6 of 11
CY7B9910–5
Typ
CY7B9920–5
Typ
Parameter
f
NOM
Description
Min
Max
30
50
80
Min
Max
30
50
80
[12]
Unit
MHz
Operating Clock
Frequency in MHz
FS = LOW
[1, 2]
FS = MID
[1, 2]
FS = HIGH
[1, 2, 3]
15
25
40
5.0
5.0
15
25
40
5.0
5.0
t
RPWH
t
RPWL
t
SKEW
t
DEV
t
PD
t
ODCV
t
ORISE
t
OFALL
t
LOCK
t
JR
REF Pulse Width HIGH
REF Pulse Width LOW
Zero Output Skew (All Outputs)
[13, 14]
Device-to-Device Skew
[8, 15]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation
[16]
Output Rise Time
[17, 18
Output Fall Time
[17, 18]
PLL Lock Time
[19]
Cycle-to-Cycle Output Jitter Peak to Peak
[8]
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
0.25
0.5
1.0
+0.5
+1.0
1.5
1.5
0.5
200
25
0.25
0.5
1.0
+0.5
+1.0
3.0
3.0
0.5
200
25
–0.5
–1.0
0.15
0.15
0.0
0.0
1.0
1.0
–0.5
–1.0
0.5
0.5
0.0
0.0
2.0
2.0
RMS
[8]
Notes
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
10.Applies to REF and FB inputs only.
11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
12.Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
13.tSKEW is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50
Ω
to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
14.tSKEW is defined as the skew between outputs.
15.tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, and
so on).
16.tODCV is the deviation of the output from a 50% duty cycle.
17.Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50
Ω
to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
18.tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B9910 or 0.8VCC and 0.2VCC for the CY7B9920.
19.tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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| CY7B9910-7SXC | Low Skew Clock Buffer |
| CY7B9910-7SXCT | Low Skew Clock Buffer |
| CY7B9920-2SC[20] | Low Skew Clock Buffer |
| CY7B9920-7SC[20] | Low Skew Clock Buffer |
| CY7B9920-7SI[20] | Low Skew Clock Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B9910-7SXC | 功能描述:鎖相環(huán) - PLL 5V 80MHz 8 TTL COM Not Programable RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B9910-7SXCT | 功能描述:鎖相環(huán) - PLL 5V 80MHz 8 TTL COM Not Programable RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B9910V-7JXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7B9911 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B9911_07 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
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