參數(shù)資料
型號: CY74FCT652TLCC
廠商: Texas Instruments, Inc.
英文描述: 8-Bit Registered Transceiver
中文描述: 8位注冊收發(fā)器
文件頁數(shù): 1/7頁
文件大?。?/td> 63K
代理商: CY74FCT652TLCC
8-Bit Registered Transceiver
CY74FCT652T
SCCS032 - September 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Function, pinout, and drive compatible with FCT and
F logic
FCT-C speed at 5.4 ns max. (Com’l)
FCT-A speed at 6.3 ns max. (Com’l)
Reduced V
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
Matched rise and fall times
Fully compatible with TTL input and output logic levels
Sink Current
Source Current
Independent register for A and B buses
Multiplexed real-time and stored data transfer
Extended commercial range of
40C to +85C
64mA
32mA
Functional Description
The FCT652T consists of bus transceiver circuits, D-type
flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal storage registers. GAB and GBA control pins are
provided to control the transceiver functions. SAB and SBA
control pins are provided to select either real-time or stored
data transfer. The circuitry used for select control will eliminate
the typical decoding glitch that occurs in a multiplexer during
the transition between stored and real-time data. A LOW input
level selects real-time data and a HIGH selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the
appropriate clock pins (CPAB or CPBA), regardless of the
select or enable control pins. When SAB and SBA are in the
real-time transfer mode, it is also possible to store data without
using the internal D-type flip-flops by simultaneously enabling
GAB and GBA. In this configuration, each output reinforces its
input. Thus, when all other data sources to the two sets of bus
lines are at high impedance, each set of bus lines will remain
at its last state.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
LogicBlock Diagram
Pin Configurations
C
D
B
1
28
27
26
4
3
2
1
5
6
7
8
9
10
13
14
15
16
17
18
25
24
23
22
21
20
11
12
19
A3
A
A
B2
B5
B1
N
N
B4
A
LCC
Top View
B3
C
D
A
1
TO 7 OTHERCHANNELS
CPAB
SAB
SBA
GBA
V
CC
CPBA
SBA
GAB
SAB
CPAB
NC
A
7
A
8
B
6
B
7
B
8
A
A
G
GAB
CPBA
B REG
A REG
1 OF 8 CHANNELS
NC
GND
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
V
CC
CPBA
SBA
15
Top View
CPAB
SAB
GAB
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
GBA
GND
SOIC/QSOP
相關(guān)PDF資料
PDF描述
CY74FCT821TDIP 8-/9-/10-Bit Bus Interface Registers
CY74FCT821TQSOP 8-/9-/10-Bit Bus Interface Registers
CY74FCT821TSOIC 8-/9-/10-Bit Bus Interface Registers
CY74FCT823TDIP 8-/9-/10-Bit Bus Interface Registers
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