參數(shù)資料
型號: CY62256LL-70PC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 256K (32K x 8) Static RAM
中文描述: 32K X 8 STANDARD SRAM, 70 ns, PDIP28
封裝: 0.600 INCH, MS-020, DIP-28
文件頁數(shù): 6/12頁
文件大小: 394K
代理商: CY62256LL-70PC
CY62256
Document #: 38-05248 Rev. *C
Page 6 of 12
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
SUPPLY
CURRENT
Read Cycle No. 2
[13, 14]
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATA
IN
VALID
NOTE
Write Cycle No. 1 (WE Controlled)
[10, 15, 16]
17
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
WE
DATA I/O
ADDRESS
CE
DATA
IN
VALID
Write Cycle No. 2 (CE Controlled)
[10, 15, 16]
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CY62256LL-70SNC 256K (32K x 8) Static RAM
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