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參數(shù)資料
| 型號： | CY62158DV30L-45ZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8-Mbit (1024K x 8) MoBL Static RAM |
| 中文描述： | 1M X 8 STANDARD SRAM, 45 ns, PDSO48 |
| 封裝： | 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, MO-142, TSOP1-48 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 325K |
| 代理商： | CY62158DV30L-45ZXI |
8-Mbit (1024K x 8) MoBL
Static RAM
CY62158DV30
MoBL
Cypress Semiconductor Corporation
Document #: 38-05391 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised June 17, 2004
Features
Very high speed: 45 ns, 55 ns and 70 ns
— Wide voltage range: 2.20V – 3.60V
Ultra-low active power
— Typical active current:1.5 mA @ f = 1 MHz
— Typical active current: 12 mA @ f = f
max
Ultra-low standby power
Easy memory expansion with CE
1
,
CE
2
,
and OE
features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 48-ball BGA, 48-pin TSOPI, and
44-pin TSOPII
Functional Description
[1]
The CY62158DV30 is a high-performance CMOS static RAMs
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption by 85% when
deselected (CE
1
HIGH or CE
2
LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is
then written into the location specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) and Output Enable (OE) LOW and Chip
Enable 2 (CE
2
) HIGH while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
LOW and CE
2
HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW). See the truth table for a complete description of read
and write modes.
Logic Block Diagram
Note:
1. For best practice recommendations, please refer to the Cypress application note entitled
System Design Guidelines
, available at http://www.cypress.com.
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
COLUMN
DECODER
R
S
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
1024K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
1
CE
1
CE
2
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62158DV30L-55BVI | 8-Mbit (1024K x 8) MoBL Static RAM |
| CY62158DV30L-55ZSXI | 8-Mbit (1024K x 8) MoBL Static RAM |
| CY62158DV30L-55ZXI | 8-Mbit (1024K x 8) MoBL Static RAM |
| CY62158DV30L-70BVI | 8-Mbit (1024K x 8) MoBL Static RAM |
| CY62158DV30L-70ZSXI | 8-Mbit (1024K x 8) MoBL Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62158DV30L-55BVI | 制造商:Rochester Electronics LLC 功能描述:8MB (1M X 8) SRAM SLOW 3.0V LOW POWER - Bulk |
| CY62158DV30L-55ZSXI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62158DV30LL-55BVI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62158DV30LL-55BVIT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62158DV30LL-55BVXI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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