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| 型號(hào)： | CY62157EV30LL-45BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8-Mbit (512K x 16) Static RAM |
| 中文描述： | 512K X 16 STANDARD SRAM, 45 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 |
| 文件頁(yè)數(shù)： | 6/14頁(yè) |
| 文件大?。?/td> | 551K |
| 代理商： | CY62157EV30LL-45BVI |
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CY62157EV30 MoBL
Document #: 38-05445 Rev. *E
Page 6 of 14
Switching Characteristics
Over the Operating Range
[13, 14]
Parameter
Description
45 ns (Ind’l/Auto-A)
Unit
Min
Max
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[18]
Read Cycle Time
45
ns
Address to Data Valid
45
ns
Data Hold from Address Change
10
ns
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW-Z
[15]
OE HIGH to High-Z
[15, 16]
CE
1
LOW and CE
2
HIGH to Low-Z
[15]
CE
1
HIGH and CE
2
LOW to High-Z
[15, 16]
CE
1
LOW and CE
2
HIGH to Power Up
CE
1
HIGH and CE
2
LOW to Power Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low-Z
[15, 17]
BLE/BHE HIGH to HIGH-Z
[15, 16]
45
ns
22
ns
5
ns
18
ns
10
ns
18
ns
0
ns
45
ns
45
ns
5
ns
18
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
45
ns
CE
1
LOW and CE
2
HIGH
to Write End
Address Setup to Write End
35
35
ns
ns
Address Hold from Write End
Address Setup to Write Start
0
0
ns
ns
WE Pulse Width
35
ns
BLE/BHE LOW to Write End
Data Setup to Write End
35
25
ns
ns
Data Hold from Write End
WE LOW to High-Z
[15, 16]
WE HIGH to Low-Z
[15]
0
ns
18
ns
10
ns
Notes
13.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
, and output loading of the specified I
/I
as shown in the
“AC Test Loads and Waveforms” on page 5
.
14.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
application note AN13842
for further clarification.
15.At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
16.t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
17.If both byte enables are toggled together, this value is 10 ns.
18.The internal write time of the memory is defined by the overlap of WE, CE
= V
, BHE, BLE or both = V
, and CE
= V
. All signals must be active to initiate a
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
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| CY62157EV30LL-45BVIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M ULTRA LO PWR HI SPD 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62157EV30LL-45BVXA | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M MOBL ULTRA Lo PWR HI SPD ASYNC 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62157EV30LL-45BVXAT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M MOBL ULTRA Lo PWR HI SPD ASYNC 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62157EV30LL45BVXI | 制造商:Cypress Semiconductor 功能描述: |
| CY62157EV30LL-45BVXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M ULTRA LO PWR HI SPD 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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