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參數(shù)資料
| 型號： | CY62157DV30LL-70ZSI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8-Mbit (512K x 16) MoBL Static RAM |
| 中文描述： | 512K X 16 STANDARD SRAM, 70 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 455K |
| 代理商： | CY62157DV30LL-70ZSI |
8-Mbit (512K x 16) MoBL
Static RAM
CY62157DV30
MoBL
Cypress Semiconductor Corporation
Document #: 38-05392 Rev. *E
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 24, 2004
Features
Temperature Ranges
—Industrial: –40°C to 85°C
—Automotive: –40°C to 125°C (Preliminary)
Very high speed: 45 ns, 55 ns and 70 ns
Wide voltage range: 2.20V – 3.60V
Pin-compatible with CY62157CV25, CY62157CV30, and
CY62157CV33
Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 12 mA @ f = f
max
Ultra-low standby power
Easy memory expansion with CE
1
, CE
2
, and OE
features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered: 48-ball BGA, 48-pin TSOPI, and
44-pin TSOPII
Functional Description
[1]
The CY62157DV30 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life
(MoBL
) in
portable applications such as cellular telephones.The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can also be put into
standby mode when deselected (CE
1
HIGH or CE
2
LOW or
both BHE and BLE are HIGH). The input/output pins (I/O
0
through I/O
15
) are placed in a high-impedance state when:
deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
18
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O
8
to I/O
15
. See the truth table for a complete description
of read and write modes.
Notes:
1. For best practice recommendations, please refer to the Cypress application note entitled
System Design Guidelines
, which is available at
http://www.cypress.com.
Logic Block Diagram
512K × 16
RAM Array
I/O0 – I/O7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA-IN DRIVERS
OE
I/O8 – I/O15
WE
BLE
BHE
A
1
A
0
A
1
A
9
A
1
A
10
Power-down
Circuit
CE
2
CE
1
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| CY62157ELL-45ZSXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 8M ULTRA LO PWR HI SPD 靜態(tài)隨機(jī)存取存儲器 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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| CY62157ELL-55BVXET | 功能描述:靜態(tài)隨機(jī)存取存儲器 8M MOBL ULTRA Lo PWR HI SPD ASYNC 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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