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參數(shù)資料
| 型號(hào)： | CY62148DV30L-70BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mb (512K x 8) MoBL Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 70 ns, PBGA36 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-36 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 195K |
| 代理商： | CY62148DV30L-70BVI |
CY62148DV30
Document #: 38-05341 Rev. *B
Page 5 of 11
Switching Characteristics
(Over the Operating Range)
[10]
Switching Waveforms
Parameter
Description
55 ns
70 ns
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[13]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[11]
OE HIGH to High Z
[11,12]
CE LOW to Low Z
[11]
CE HIGH to High Z
[11, 12]
CE LOW to Power-up
CE HIGH to Power-up
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
10
10
55
25
70
35
5
5
20
25
10
10
20
25
0
0
55
70
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[11, 12]
WE HIGH to Low Z
[11]
55
40
40
0
0
40
25
0
70
45
45
0
0
45
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
10
10
Notes:
10. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2,
input pulse levels of 0 to V
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
11.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
HZWE
is less than t
LZWE
for any given device.
12. t
, t
, and t
transitions are measured when the output enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE = V
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
14. Device is continuously selected. OE, CE = V
IL
.
15. WE is HIGH for read cycle.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
Read Cycle No. 1 (Address Transition Controlled)
[14, 15]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62148DV30L-70BVXI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-70SXI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-70ZSXI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30LL-70BVI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30LL-70BVXI | 4-Mb (512K x 8) MoBL Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62148DV30L-70BVXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-70SXI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62148DV30L-70ZSXI | 制造商:Cypress Semiconductor 功能描述: |
| CY62148DV30LL | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (512K x 8) MoBL㈢ Static RAM |
| CY62148DV30LL-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (512K x 8) MoBL? Static RAM |
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