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參數(shù)資料
| 型號： | CY62148B |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512K x 8 Static RAM |
| 中文描述： | 為512k × 8靜態(tài)RAM |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 189K |
| 代理商： | CY62148B |
CY62148B MoBL
Document #: 38-05039 Rev. *B
Page 5 of 11
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
Conditions
Min.
2.0
Typ.
[3]
Max.
Unit
V
μ
A
μ
A
ns
ns
V
CC
for Data Retention
Data Retention Current
Com
’
l
Ind
’
l
LL
LL
No input may exceed
V
CC
+ 0.3V
V
CC
= V
DR
= 3.0V
CE > V
CC
–
0.3V
V
IN
> V
CC
–
0.3V or
V
IN
< 0.3V
20
20
t
CDR[4]
t
R[9]
Chip Deselect to Data Retention Time
Operation Recovery Time
0
t
RC
Data Retention Waveform
Switching Waveforms
Read Cycle No.1
[10, 11]
Read Cycle No. 2 (OE Controlled)
[11, 12]
Notes:
9.
10. Device is continuously selected. OE, CE = V
IL
.
11.
WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Full Device operatin requires linear V
ramp from V
DR
to V
CC(min)
> 100
μ
s or stable at V
cc(min)
> 100
μ
s.
3.0V
3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
I
SB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
相關PDF資料 |
PDF描述 |
|---|---|
| CY62148BLL-70SC | 512K x 8 Static RAM |
| CY62148BLL-70SI | 512K x 8 Static RAM |
| CY62148BLL-70ZC | 512K x 8 Static RAM |
| CY62148BLL-70ZI | 512K x 8 Static RAM |
| CY62148BLL-70ZRC | 512K x 8 Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY62148B_06 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (512K x 8) Static RAM |
| CY62148BLL-55SC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| CY62148BLL-55SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| CY62148BLL-55ZC | 制造商:Cypress Semiconductor 功能描述:SLOW 5.0V SUPER LOW POWER 512K X 8 SRAM - Bulk |
| CY62148BLL-55ZCT | 制造商:Cypress Semiconductor 功能描述:SLOW 5.0V SUPER LOW POWER 512K X 8 SRAM - Tape and Reel |
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