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參數(shù)資料
| 型號： | CY62148 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512K x 8 Static RAM(512K x 8 靜態(tài)RAM) |
| 中文描述： | 為512k × 8靜態(tài)存儲器（為512k × 8靜態(tài)RAM）的 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 157K |
| 代理商： | CY62148 |
CY62148
3
PRELIMINARY
Capacitance
[4]
Parameter
Description
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
6
8
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
AC Test Loads and Waveforms
Switching Characteristics
[5]
Over the Operating Range
62148
–
55
Min.
62148
–
70
Min.
62148
–
100
Min.
Parameter
Description
Max.
Max.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
Notes:
4.
Tested initially and after any design or process changes that may affect these parameters.
5.
Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
6.
t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
8.
The internal write time of the memory is defined by the overlap of CE
LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Read Cycle Time
55
70
100
ns
Address to Data Valid
55
70
100
ns
Data Hold from Address Change
10
10
10
ns
CE LOW to Data Valid
55
70
100
ns
OE LOW to Data Valid
OE LOW to Low Z
[7]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High Z
[6, 7]
20
35
50
ns
5
5
5
ns
20
25
30
ns
10
10
10
ns
20
25
30
ns
CE LOW to Power-Up
0
0
0
ns
CE HIGH to Power-Down
55
70
100
ns
Write Cycle Time
55
70
100
ns
CE LOW to Write End
45
60
80
ns
Address Set-Up to Write End
45
60
80
ns
Address Hold from Write End
0
0
0
ns
Address Set-Up to Write Start
0
0
0
ns
WE Pulse Width
45
55
60
ns
Data Set-Up to Write End
25
25
25
ns
62148-4
62148-5
90%
10%
5.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
≤
3 ns
≤
3 ns
OUTPUT
R1 1838
R2
994
645
Equivalent to:
THEVENIN EQUIVALENT
1.75V
R1 1838
(a)
62148-3
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
994
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| CY62148-55 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 8 Static RAM |
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