參數(shù)資料
型號: CY62147VLL-70ZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4M (256K x 16) Static RAM
中文描述: 256K X 16 STANDARD SRAM, 70 ns, PDSO44
封裝: TSOP2-44
文件頁數(shù): 6/9頁
文件大?。?/td> 170K
代理商: CY62147VLL-70ZI
CY62147V MoBL
Document #: 38-05050 Rev. *A
Page 6 of 9
Notes:
15. Data I/O is high-impedance if OE = V
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
Write Cycle No. 2 (CE Controlled)
[8, 15, 16]
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
WE
DATA
IN
VALID
t
BW
t
PWE
DATA I/O
ADDRESS
CE
BHE/BLE
DATA I/O
ADDRESS
t
HD
t
SD
t
LZWE
t
SA
t
HA
t
AW
t
WC
CE
WE
t
HZWE
DATA
IN
VALID
Write Cycle No. 3 (WE Controlled, OE LOW)
[11, 16]
NOTE 17
BHE/BLE
t
BW
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