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參數(shù)資料
| 型號： | CY62147DV30LL-55BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 55 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 359K |
| 代理商： | CY62147DV30LL-55BVI |
CY62147DV30
Document #: 38-05340 Rev. *F
Page 5 of 12
Switching Characteristics
Over the Operating Range
[14]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[17]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Description
45 ns
[11]
Min.
55 ns
70 ns
Unit
Max.
Min.
Max.
Min.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[15]
OE HIGH to High Z
[15, 16]
CE LOW to Low Z
[15]
CE HIGH to High Z
[15, 16]
CE LOW to Power-Up
CE HIGH to Power-Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[15]
BLE/BHE HIGH to HIGH Z
[15, 16]
45
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
55
70
10
10
10
45
25
55
25
70
35
5
5
5
15
20
25
10
10
10
20
20
25
0
0
0
45
45
55
55
70
70
10
10
10
15
20
25
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[15, 16]
WE HIGH to Low-Z
[15]
45
40
40
0
0
35
40
25
0
55
40
40
0
0
40
40
25
0
70
60
60
0
0
45
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
20
25
10
10
10
Notes:
14.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
15.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
16.t
, t
, t
, and t
transitions are measured when the outputs enter a high impedence state.
17.The internal Write time of the memory is defined by the overlap of WE, CE
= V
, BHE and/or BLE = V
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62147DV30LL-55BVIT | 制造商:Rochester Electronics LLC 功能描述:4MB (256K X 16) 3.0V SUPER LOW POWER SLOW SRAM - Bulk |
| CY62147DV30LL-55BVXI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY62147DV30LL-55ZSI | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 2.5V/3.3V 4MBIT 256KX16 55NS 44TSOP-II - Bulk |
| CY62147DV30LL-55ZSXI | 制造商:Rochester Electronics LLC 功能描述:4MB (256K X 16) 3.0V SUPER LOW POWER SLOW - Bulk |
| CY62147DV30LL-70BVI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:4MB (256K X 16) 3.0V SUPER LOW POWER SLOW SRAM - Bulk |
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