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參數(shù)資料
| 型號： | CY62147CV33LL-55BAI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 16 Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 55 ns, PBGA48 |
| 封裝： | 7 X 8.50 MM, 1.20 MM HEIGHT, FINE PITCH, TBGA-48 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 272K |
| 代理商： | CY62147CV33LL-55BAI |
CY62147CV18 MoBL2
Document #: 38-05011 Rev. *B
Page 5 of 12
Switching Characteristics
Over the Operating Range
[8]
55 ns
70 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
[11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
8.
Test conditions assume signal transition time of 3ns or less, timing reference levels of V
CC(typ)
/2, input pulse levels of 0 to V
CC(typ)
, and output loading of the
specified I
/I
and 30-pF load capacitance.
9.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
11.
The internal write time of the memory is defined by the overlap of WE, CE
= V
, BHE and/or BLE =V
. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[9]
OE HIGH to High Z
[9, 10]
CE LOW to Low Z
[9]
CE HIGH to High Z
[9, 10]
CE LOW to Power-Up
CE HIGH to Power-Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[9]
BLE/BHE HIGH to High Z
[9, 10]
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
10
10
55
25
70
35
5
5
20
25
5
10
20
25
0
0
55
55
70
70
5
5
20
25
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[9, 10]
WE HIGH to Low Z
[9]
55
40
40
0
0
40
40
25
0
70
60
60
0
0
50
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
25
5
10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62147CV33LL-55BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 4M-Bit 256K x 16 55ns 48-Pin FBGA T/R |
| CY62147CV33LL-55BVI | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3.3V 4MBIT 256KX16 55NS 48VFBGA - Bulk |
| CY62147CV33LL-55BVIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3.3V 4MBIT 256KX16 55NS 48VFBGA - Tape and Reel |
| CY62147CV33LL-70BAI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 4M-Bit 256K x 16 70ns 48-Pin FBGA |
| CY62147CV33LL-70BVI | 制造商:Rochester Electronics LLC 功能描述:4MB (256KX16) SRAM SLOW 3.3V SUPER LOW POWER - Bulk 制造商:Cypress Semiconductor 功能描述: |
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