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參數(shù)資料
| 型號(hào)： | CY62147CV18LL-55BAI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 16 Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 55 ns, PBGA48 |
| 封裝： | 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 272K |
| 代理商： | CY62147CV18LL-55BAI |
CY62147CV18 MoBL2
Document #: 38-05011 Rev. *B
Page 4 of 12
Notes:
6.
7.
Full device operation requires linear V
ramp from V
to V
>
100
μ
s or stable at V
>
100
μ
s.
BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
AC Test Loads and Waveforms
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
Equivalent to:
TH
é
VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise Time:
1 V/ns
Fall Time:
1 V/ns
Parameters
R1
R2
R
TH
V
TH
1.8V
13500
10800
6000
0.80
UNIT
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
Description
Conditions
Min.
1.0
Typ.
[4]
Max.
1.95
8
Unit
V
μ
A
V
CC
for Data Retention
I
CCDR
Data Retention Current
V
CC
= 1.0V
CE > V
CC
0.2V,
V
IN
> V
CC
0.2V or V
IN
< 0.2V
1
t
CDR[5]
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
ns
t
R[6]
t
RC
ns
Data Retention Waveform
[7]
V
CC(min.)
t
R
V
CC(min.)
t
CDR
V
DR
> 1.0 V
DATA RETENTION MODE
CE or
V
CC
BHE,BHE
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY62147CV18LL-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:256K x 16 Static RAM |
| CY62147CV18LL-70BAI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
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| CY62147CV18LL-70BKI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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