參數(shù)資料
型號: CY62146DV30L-70BVI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4-Mbit (256K x 16) Static RAM
中文描述: 256K X 16 STANDARD SRAM, 70 ns, PBGA48
封裝: 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
文件頁數(shù): 7/11頁
文件大?。?/td> 406K
代理商: CY62146DV30L-70BVI
CY62146DV30
Document #: 38-05339 Rev. *A
Page 7 of 11
Write Cycle No. 1 (WE Controlled)
[15, 19, 20]
Write Cycle No. 2 (CE
Controlled)
[15, 19, 20]
Notes:
19.Data I/O is high impedance if OE = V
.
20.If CE goes HIGH simultaneously with WE = V
, the output remains in a high-impedance state.
21.During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATA
IN
NOTE 21
BHE/BLE
t
BW
t
SCE
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
CE
ADDRESS
WE
DATA I/O
OE
NOTE 21
BHE/BLE
t
BW
t
SA
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