- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380165 > CY62138F (Cypress Semiconductor Corp.) 2-Mbit (256K x 8) Static RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | CY62138F |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2-Mbit (256K x 8) Static RAM |
| 中文描述： | 2兆位（256K × 8）靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 776K |
| 代理商： | CY62138F |
Document #: 001-13194 Rev. *A
Page 5 of 10
CY62138F MoBL
Switching Characteristics
(Over the Operating Range)
[11]
Parameter
Description
45 ns
Unit
Min
Max
Read Cycle
t
RC
Read Cycle Time
45
ns
t
AA
Address to Data Valid
45
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
45
ns
t
DOE
22
ns
t
LZOE
OE LOW to Low-Z
[12]
5
ns
t
HZOE
OE HIGH to High-Z
[12, 13]
18
ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low Z
[12]
CE
1
HIGH or CE
2
LOW to High-Z
[12, 13]
CE
1
LOW and CE
2
HIGH to power up
CE
1
HIGH or CE
2
LOW to power down
10
ns
t
HZCE
18
ns
t
PU
0
ns
t
PD
Write Cycle
[14]
45
ns
t
WC
Write Cycle Time
45
ns
t
SCE
CE
1
LOW and CE
2
HIGH to Write End
Address Setup to Write End
35
ns
t
AW
35
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Setup to Write Start
0
ns
t
PWE
WE Pulse Width
35
ns
t
SD
Data Setup to Write end
25
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High-Z
[12, 13]
18
ns
t
LZWE
WE HIGH to Low-Z
[12]
10
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the
AC Test Loads and Waveforms on page 4
.
12.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
13.t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
14.The internal write time of the memory is defined by the overlap of WE, CE
= V
, and CE
= V
. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62138FLL-45SXI | 2-Mbit (256K x 8) Static RAM |
| CY62138FLL-45ZSXI | 2-Mbit (256K x 8) Static RAM |
| CY62138VN | 256K x 8 Static RAM |
| CY62138VNLL-70BAI | 256K x 8 Static RAM |
| CY62138V | 256K x 8 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62138F_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256K x 8) Static RAM |
| CY62138F_10 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256K x 8) Static RAM |
| CY62138F_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256 K x 8) Static RAM Automatic power down when deselected |
| CY62138F_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256 K x 8) Static RAM |
| CY62138FLL | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256K x 8) Static RAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。