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參數(shù)資料
| 型號： | CY62137VLL-55ZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2-Mbit (128K x 16) Static RAM |
| 中文描述： | 128K X 16 STANDARD SRAM, 55 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 214K |
| 代理商： | CY62137VLL-55ZI |
CY62137V MoBL
Document #: 38-05051 Rev. *B
Page 5 of 11
Switching Characteristics
Over the Operating Range
[6]
Parameter
Description
55 ns
70 ns
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE (9)
t
HZBE
Write Cycle
[10, 11]
Read Cycle Time
55
70
ns
Address to Data Valid
55
70
ns
Data Hold from Address Change
10
10
ns
CE LOW to Data Valid
55
70
ns
OE LOW to Data Valid
OE LOW to Low-Z
[7]
OE HIGH to High-Z
[7, 8]
CE LOW to Low-Z
[7]
CE HIGH to High-Z
[7, 8]
25
35
ns
5
5
ns
25
25
ns
10
10
ns
25
25
ns
CE LOW to Power-up
0
0
ns
CE HIGH to Power-down
55
70
ns
BHE / BLE LOW to Data Valid
55
70
ns
BHE / BLE LOW to Low-Z
5
5
ns
BHE / BLE HIGH to High-Z
25
25
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
t
BW
Write Cycle Time
55
70
ns
CE LOW to Write End
45
60
ns
Address Set-up to Write End
45
60
ns
Address Hold from Write End
0
0
ns
Address Set-up to Write Start
0
0
ns
WE Pulse Width
40
50
ns
Data Set-up to Write End
25
30
ns
Data Hold from Write End
WE LOW to High-Z
[7, 8]
WE HIGH to Low-Z
[7]
0
0
ns
20
25
ns
5
10
ns
BHE / BLE LOW to End of Write
50
60
ns
Notes:
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to V
CC
typ., and output loading of the specified
I
/I
and 30 pF load capacitance.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
t
, t
, and t
are specified with C
= 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
If both byte enables are toggled together this value is 10 ns.
9.
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11.
The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
7.
8.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62137VLL-55ZXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62137VLL-70BAI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述:Static RAM, 128Kx16, 48 Pin, Plastic, BGA |
| CY62137VLL-70ZE | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62137VLL-70ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62137VLL-70ZSXE | 功能描述:IC SRAM 2MBIT 70NS 44TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:MoBL® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
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