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參數(shù)資料
| 型號： | CY62137CV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 32-Bit Transparent D-Type Latch with 3-State Outputs 96-LFBGA -40 to 85 |
| 中文描述： | 200萬（128K的× 16）靜態(tài)RAM |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 227K |
| 代理商： | CY62137CV |
2M (128K x 16) Static RAM
CY62137CV25/30/33 MoBL
CY62137CV MoBL
Cypress Semiconductor Corporation
Document #: 38-05201 Rev. *D
3901 North First Street
San Jose
CA 95134
Revised September 20, 2002
408-943-2600
Features
Very high speed: 55 ns and 70 ns
Voltage range:
—
CY62137CV25: 2.2V
–
2.7V
—
CY62137CV30: 2.7V
–
3.3V
—
CY62137CV33: 3.0V
–
3.6V
—
CY62137CV: 2.7V
–
3.6V
Pin-compatible with the CY62137V
Ultra-low active power
—
Typical active current: 1.5 mA @ f = 1 MHz
—
Typical active current: 5.5 mA @ f = f
max
(70-ns
speed)
Low and ultra-low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 48-ball FBGA
Functional Description
[1]
The CY62137CV25/30/33 and CY62137CV are high-perfor-
mance CMOS static RAMs organized as 128K words by 16
bits. These devices feature advanced circuit design to provide
ultra-low active current. This is ideal for providing More Battery
Life
(MoBL
) in portable applications such as cellular tele-
phones. The devices also has an automatic power-down fea-
ture that significantly reduces power consumption by 80%
when addresses are not toggling. The device can also be put
into standby mode reducing power consumption by more than
99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input/output pins (I/O
0
through I/O
15
) are placed
in a high-impedance state when: deselected (CE HIGH), out-
puts are disabled (OE HIGH), both Byte High Enable and Byte
Low Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1.
For best practice recommendations, please refer to the Cypress application note
“
System Design Guidelines
”
on http://www.cypress.com.
Logic Block Diagram
128K x 16
RAM Array
2048 x 1024
I/O
0
–
I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
I/O
8
–
I/O
15
CE
WE
BHE
A
1
A
0
A
9
Power-down
Circuit
BHE
BLE
CE
A
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62137CV30LL-55BAI | 2M (128K x 16) Static RAM |
| CY62137CV30LL-55BVI | 2M (128K x 16) Static RAM |
| CY62137CV33LL-55BAI | 2M (128K x 16) Static RAM |
| CY62137CVSL-70BAI | 2M (128K x 16) Static RAM |
| CY62137CVSL-70BVI | 2M (128K x 16) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62137CV18 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 16 Static RAM |
| CY62137CV18_02 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 16 Static RAM |
| CY62137CV18LL-55BAI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 1.8V 2M-Bit 128K x 16 55ns 48-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62137CV18LL-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 16 Static RAM |
| CY62137CV18LL-70BAI | 制造商:Rochester Electronics LLC 功能描述:2MB (128K X 16)- SLOW ASYNCH SRAM - Bulk |
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